JPH044778B2 - - Google Patents
Info
- Publication number
- JPH044778B2 JPH044778B2 JP9714385A JP9714385A JPH044778B2 JP H044778 B2 JPH044778 B2 JP H044778B2 JP 9714385 A JP9714385 A JP 9714385A JP 9714385 A JP9714385 A JP 9714385A JP H044778 B2 JPH044778 B2 JP H044778B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- interference
- interference wave
- phase
- band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Noise Elimination (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は干渉波抽出回路に関し、特にマイクロ
波デイジタル伝送システムにおけるデイジタル変
調波からFM干渉波を除去する干渉波除去装置に
用いられる干渉波抽出回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interference wave extraction circuit, and particularly to an interference wave extraction circuit used in an interference wave removal device that removes FM interference waves from digitally modulated waves in a microwave digital transmission system. Regarding circuits.
マイクロ波デイジタル伝送システムが同一周波
数帯のマイクロ波FM伝送システムから干渉を受
ける場合、マイクロ波デイジタル伝送システムに
干渉波除去装置を付加してFM干渉波の影響を除
く必要がある。
If a microwave digital transmission system receives interference from a microwave FM transmission system in the same frequency band, it is necessary to add an interference wave removal device to the microwave digital transmission system to remove the influence of the FM interference waves.
このために用いられる従来の干渉波除去装置の
２例として、特開昭−131852号公報に提案されて
いるものおよび特開昭58−131853号公報に提案さ
れているものがある。 Two examples of conventional interference wave removal devices used for this purpose are one proposed in Japanese Patent Laid-Open No. 131852/1982 and one proposed in Japanese Patent Laid-Open No. 131853/1982.
第２図はこれら干渉波除去装置の従来例の概要
を示すブロツク図である。 FIG. 2 is a block diagram showing an outline of a conventional example of these interference wave removal devices.
第２図に示す干渉波除去装置は、干渉波を含む
入力信号１０１を入力し抽出干渉信号２０２を出
力する干渉波抽出回路１と、抽出干渉信号２０
２・振幅誤差信号１０６・位相誤差信号１０７を
入力し相殺信号１０３を出力する振幅位相制御回
路２と、入力信号１０１・相殺信号１０３を入力
し主信号１０４を出力する減算器３と、主信号１
０４・抽出干渉信号２０２を入力し出力信号１０
５・振幅誤差信号１０６・位相誤差信号１０７を
出力する制御信号発生回路４とを具備して構成さ
れている。振幅位相制御回路２は、抽出信号２０
２・振幅誤差信号１０６を入力し可変移相器２２
に信号を出力する可変減衰器２１と、可変減衰器
２１の出力と位相誤差信号１０７とを入力し相殺
信号１０３を出力する可変移相器２２とを備えて
構成されている。 The interference wave removal device shown in FIG.
2. Amplitude and phase control circuit 2 which inputs amplitude error signal 106 and phase error signal 107 and outputs cancellation signal 103; subtracter 3 which inputs input signal 101 and cancellation signal 103 and outputs main signal 104; and main signal. 1
04・Input extracted interference signal 202 and output signal 10
5. The control signal generation circuit 4 outputs an amplitude error signal 106 and a phase error signal 107. The amplitude phase control circuit 2 extracts the extracted signal 20
2. Input the amplitude error signal 106 to the variable phase shifter 22
The variable attenuator 21 outputs a signal to the output signal, and the variable phase shifter 22 inputs the output of the variable attenuator 21 and a phase error signal 107 and outputs a cancellation signal 103.
次に第２図に示す干渉波除去装置の動作を説明
する。 Next, the operation of the interference wave removal device shown in FIG. 2 will be explained.
干渉波抽出回路１は、入力信号１０１に含まれ
る干渉波を抽出干渉信号２０２として抽出する。
振幅位相制御回路２は、抽出干渉信号２０２の振
幅・位相を可変減衰器２１・可変移相器２２で振
幅誤差信号１０６・位相誤差信号１０７により制
御して相殺信号１０３を出力する。減衰器３は、
入力信号１０１から相殺信号２０２を減算するこ
とにより入力信号１０１に含まれる干渉波を抑圧
して主信号１０４を出力する。制御信号発生回路
４は、主信号１０４に残留する干渉波と抽出干渉
信号２０２とから相殺信号１０３の振幅・位相誤
差に対応する振幅誤差信号１０６・位相誤差信号
１０７を作りだす。振幅誤差信号１０６・位相誤
差信号１０７が相殺信号１０３の振幅・位相誤差
を補正するので、主信号１０４に残留する干渉波
が抑圧される。なお特開昭58−131852号公報に提
案されている干渉波除去装置では、出力信号１０
５は主信号１０４が検波・再生されたデータ信号
であり、特開昭58−131853号公報に提案されてい
る干渉波除去装置では、出力信号１０５は主信号
１０４そのものである。 The interference wave extraction circuit 1 extracts the interference wave included in the input signal 101 as an extracted interference signal 202.
The amplitude and phase control circuit 2 controls the amplitude and phase of the extracted interference signal 202 using a variable attenuator 21 and a variable phase shifter 22 using an amplitude error signal 106 and a phase error signal 107, and outputs a cancellation signal 103. Attenuator 3 is
By subtracting the cancellation signal 202 from the input signal 101, the interference waves contained in the input signal 101 are suppressed and the main signal 104 is output. The control signal generation circuit 4 generates an amplitude error signal 106 and a phase error signal 107 corresponding to the amplitude and phase errors of the cancellation signal 103 from the interference wave remaining in the main signal 104 and the extracted interference signal 202. Since the amplitude error signal 106 and phase error signal 107 correct the amplitude and phase error of the cancellation signal 103, the interference wave remaining in the main signal 104 is suppressed. Note that in the interference wave removal device proposed in Japanese Patent Application Laid-Open No. 58-131852, the output signal 10
5 is a data signal obtained by detecting and reproducing the main signal 104, and in the interference wave removal device proposed in Japanese Patent Application Laid-Open No. 131853/1980, the output signal 105 is the main signal 104 itself.
第３図は、干渉波抽出回路１の一具体例として
特開昭58−131852号公報に記載されているものを
示すブロツク図である。 FIG. 3 is a block diagram showing a specific example of the interference wave extraction circuit 1 described in Japanese Patent Laid-Open No. 131852/1983.
第３図に示す干渉波抽出回路１は、帯域波器
１１と位相比較器２１・低域波器１３・電圧制
御発振器１４を有する位相同期回路とを備えて構
成されている。抽出干渉信号２０２は、位相同期
回路のループにより、帯域波器１１の出力に含
まれる干渉波に位相同期されるので入力信号１０
１に含まれる干渉波を抽出したものとなる。帯域
波器１１は、入力信号１０１の干渉波以外の成
分を抑圧して位相比較器１２の入力の一方のＣ／
Ｎを高めて位相同期ループの動作を安定にするも
のであり、狭帯域である必要がある。 The interference wave extraction circuit 1 shown in FIG. 3 includes a band wave generator 11 and a phase synchronization circuit having a phase comparator 21, a low frequency wave generator 13, and a voltage controlled oscillator 14. The extracted interference signal 202 is phase-locked to the interference wave included in the output of the bandpass filter 11 by the loop of the phase-locked circuit, so that the extracted interference signal 202 is synchronized with the input signal 10.
This is an extracted interference wave included in 1. The bandpass filter 11 suppresses components other than interference waves of the input signal 101 and converts one of the inputs of the phase comparator 12 into C/
It increases N to stabilize the operation of the phase-locked loop, and needs to have a narrow band.
第２図に示す干渉波除去装置においては、入力
信号１０１に含まれる干渉波が点ａから点ｂに到
達するまでの時間t1と、点ａから干渉波抽出回路
１・振幅位相制御回路２を経て相殺信号１０３に
なり点ｃに到達するまでの時間t2とが等しくなる
ように調整されている。しかし干渉波抽出回路１
に含まれる帯域波器１１は既に説明したように
狭帯域であり遅延時間が大きいので、その通過位
相は、干渉波の周波数が変動すると大きく変動
し、抽出干渉信号２０２の位相も動じく大きく変
動して可変移相器２２で補正し得ないほどにな
り、干渉波の抑圧度が劣化する。 In the interference wave removal device shown in FIG. 2, the time t1 for the interference wave included in the input signal 101 to arrive from point a to point b, and the interference wave extraction circuit 1 and amplitude phase control circuit 2 from point a to The signal is adjusted so that the time t 2 required for the signal to become the cancellation signal 103 and reach the point c is equal to the time t 2 . However, interference wave extraction circuit 1
As already explained, the band waver 11 included in the waveform generator 11 has a narrow band and a large delay time, so its passing phase fluctuates greatly when the frequency of the interference wave fluctuates, and the phase of the extracted interference signal 202 also fluctuates greatly. This becomes so large that it cannot be corrected by the variable phase shifter 22, and the degree of interference wave suppression deteriorates.
以上説明したように従来の干渉波抽出回路は干
渉波の周波数が変動すると通過位相も変動するの
で、これを用いる干渉波除去装置の干渉波抑圧度
が劣化するという欠点がある。 As explained above, in the conventional interference wave extracting circuit, when the frequency of the interference wave changes, the passing phase also changes, so there is a drawback that the degree of interference wave suppression of the interference wave removing device using this circuit deteriorates.
本発明が解決しようとする問題点、いいかえれ
ば本発明の目的は、上記の欠点を解決して干渉波
の周波数が変動しても通過位相が変動しない干渉
波抽出回路を提供することにある。
The problem to be solved by the present invention, in other words, the purpose of the present invention is to solve the above-mentioned drawbacks and provide an interference wave extraction circuit in which the passing phase does not change even if the frequency of the interference wave changes.
本発明の干渉波抽出回路は、干渉波を含む入力
信号を入力し、前記干渉波以外の成分を抑圧する
帯域波器と、前記帯域波器の出力と遅延手段
の出力とを入力し、これら入力の位相を比較して
誤差信号を出力する位相比較器と、前記誤差信号
を入力し、この入力の帯域を制限する低域波器
と、前記低域波器の出力を入力し、この入力に
より制御される周波数の抽出干渉信号を出力する
可変発振器と、前記抽出干渉信号を入力し、この
入力に前記帯域波器の遅延と等価な遅延を与え
る前記遅延手段とを備えて構成される。
The interference wave extracting circuit of the present invention inputs an input signal including an interference wave, inputs a band waver for suppressing components other than the interference wave, and inputs an output of the band wave generator and an output of a delay means. a phase comparator that compares the phases of inputs and outputs an error signal; a low-pass filter that inputs the error signal and limits the band of this input; A variable oscillator that outputs an extracted interference signal of a frequency controlled by a variable oscillator, and the delay means that inputs the extracted interference signal and provides a delay equivalent to the delay of the band wave generator to this input.
以下実施例を示す図面を参照して本発明につい
て詳細に説明する。
The present invention will be described in detail below with reference to drawings showing embodiments.
第１図は、本発明の干渉波抽出回路の一実施例
を示すブロツク図である。 FIG. 1 is a block diagram showing an embodiment of the interference wave extraction circuit of the present invention.
第１図に示す実施例は、外部から入力信号１０
１を入力する帯域波器１１と、帯域波器１
１，１５の出力を入力する位相比較器１２と、位
相比較器１２の出力を入力する低域波器１３
と、低域波器１３の出力を入力し抽出干渉信号
１０２を外部に出力する電圧制御発振器１４と、
抽出干渉信号１０２を分岐して入力する帯域波
器１５とを備えて構成されている。 The embodiment shown in FIG.
Bandwidth wave generator 11 inputting 1 and Bandwidth wave generator 1
A phase comparator 12 that inputs the outputs of 1 and 15, and a low frequency filter 13 that inputs the output of the phase comparator 12.
and a voltage controlled oscillator 14 which inputs the output of the low-frequency wave generator 13 and outputs the extracted interference signal 102 to the outside.
It is configured to include a bandpass filter 15 that branches the extracted interference signal 102 and inputs it.
次に第１図に示す実施例の動作について説明す
る。 Next, the operation of the embodiment shown in FIG. 1 will be explained.
帯域波器１１は、入力信号１０１の干渉波以
外の成分を抑圧し、出力における干渉波のＣ／Ｎ
を向上させる。位相比較器１２は、帯域波器１
１，１５の出力を位相比較して、誤差信号を出力
する。低域波器１３は誤差信号の帯域を制限す
る。電圧制御発振器１４は、低域波器１３の出
力により制御される周波数の発振出力を抽出干渉
信号１０２として出力する。抽出干渉信号１０２
は帯域波器１５を経て位相比較器１２に入力さ
れる。 The bandpass filter 11 suppresses components other than the interference waves of the input signal 101, and reduces the C/N of the interference waves at the output.
improve. The phase comparator 12 is a band wave detector 1
The phases of the outputs of 1 and 15 are compared and an error signal is output. The low frequency filter 13 limits the band of the error signal. The voltage controlled oscillator 14 outputs an oscillation output at a frequency controlled by the output of the low frequency generator 13 as an extracted interference signal 102. Extracted interference signal 102
is input to the phase comparator 12 via the bandpass filter 15.
抽出干渉信号１０２は、位相比較器１２・低域
波器１３・電圧制御発振器１４・帯域波器１
５から構成される位相同期ループにより、帯域
波器１１の出力に含まれる干渉波に位相同期され
るので、入力信号１０１に含まれる干渉波に一致
したものとなる。位相同期ループの帯域幅を決定
するのは低域波器１３であり、帯域波器１１
は、位相比較器１２の入力の一方のＣ／Ｎを向上
させて位相同期ループの動作を安定にさせる機能
をはたす。帯域波器１１の通過帯域幅を、位相
同期ループが不安定にならない程度に狭くする必
要がある。帯域波器１５の遅延特性を帯域波
器１１の遅延特性と同等にする。そうすれば、入
力信号１０１に含まれる干渉波に対する帯域波
器１１の通過位相と、抽出干渉信号１０２に対す
る帯域波器１２の通過位相とは、干渉波の周波
数が変動しても一致しており、これら両通過位相
は位相比較器１２で相殺されるから、入力信号１
０１に含まれる干渉波が抽出干渉波１０２として
出力する間の通過位相は干渉波の周波数が変動し
ても変動しない。 The extracted interference signal 102 is extracted by a phase comparator 12, a low frequency generator 13, a voltage controlled oscillator 14, and a band frequency generator 1.
5, the phase synchronization is performed with the interference wave included in the output of the bandpass filter 11, so that it matches the interference wave included in the input signal 101. The band width of the phase-locked loop is determined by the low frequency wave generator 13, and the band wave generator 11
functions to improve the C/N of one of the inputs of the phase comparator 12 and stabilize the operation of the phase locked loop. It is necessary to narrow the passband width of the bandpass filter 11 to such an extent that the phase-locked loop does not become unstable. The delay characteristics of the band wave generator 15 are made equal to the delay characteristics of the band wave generator 11. In this way, the passing phase of the bandpass filter 11 for the interference wave included in the input signal 101 and the passing phase of the bandpass converter 12 for the extracted interference signal 102 will match even if the frequency of the interference wave changes. , these two passing phases are canceled by the phase comparator 12, so that the input signal 1
The passing phase during which the interference wave included in the interference wave 01 is output as the extracted interference wave 102 does not change even if the frequency of the interference wave changes.
なお、帯域波器１５は、帯域波器１１の遅
延特性を補償する機能をはたすものであるから、
帯域波器１５のかわりに、遅延特性が帯域波
器１１のそれと同等である遅延回路を用いること
もできる。 Note that since the band waver 15 functions to compensate for the delay characteristics of the band wave waver 11,
Instead of the band wave generator 15, a delay circuit whose delay characteristics are equivalent to that of the band wave generator 11 may be used.
以上詳細に説明したように、本発明を用いれば
干渉波の周波数が変動しても通過位相が変動しな
い干渉波抽出回路を提供できるという効果があ
り、干渉波除去装置に本発明の干渉波抽出回路を
用いれば干渉波の周波数の変動による干渉波抑圧
度の劣化を防止することができるという効果があ
る。
As explained in detail above, the present invention has the effect of providing an interference wave extraction circuit in which the passing phase does not change even if the frequency of the interference wave changes, and the interference wave extraction circuit of the present invention can be used in an interference wave removal device. The use of the circuit has the effect of preventing deterioration of the degree of interference wave suppression due to fluctuations in the frequency of the interference waves.
第１図は本発明の干渉波抽出回路の一実施例を
示すブロツク図、第２図は従来の干渉波除去装置
の２例の概要を示すブロツク図、第３図は第２図
における干渉波抽出回路１の一具体例を示すブロ
ツク図である。
１１，１５……帯域波器、１２……位相比較
器、１３……低域波器、１４……電圧制御発振
器。
FIG. 1 is a block diagram showing an embodiment of the interference wave extraction circuit of the present invention, FIG. 2 is a block diagram showing an outline of two examples of a conventional interference wave removal device, and FIG. 3 is a block diagram showing the interference wave in FIG. 2. 1 is a block diagram showing a specific example of an extraction circuit 1. FIG. 11, 15... Bandwidth wave generator, 12... Phase comparator, 13... Low frequency wave generator, 14... Voltage controlled oscillator.
Claims (1)
以外の成分を抑圧する帯域波器と、 前記帯域波器の出力と遅延手段の出力とを入
力し、これら入力の位相を比較して誤差信号を出
力する位相比較器と、 前記誤差信号を入力し、この入力の帯域を制限
する低域波器と、 前記低域波器の出力を入力し、この入力によ
り制御される周波数の抽出干渉信号を出力する可
変発振器と、 前記抽出干渉信号を入力し、この入力に前記帯
域波器の遅延と等価な遅延を与える前記遅延手
段と を備えることを特徴とする干渉波抽出回路。[Scope of Claims] 1. A band waver which inputs an input signal including an interference wave and suppresses components other than the interference wave; an output of the band wave generator and an output of a delay means are input, and the output of these input signals is inputted. a phase comparator that compares phases and outputs an error signal; a low-pass filter that inputs the error signal and limits the band of this input; and a low-pass filter that inputs the output of the low-pass filter and controls by this input. an interference wave characterized by comprising: a variable oscillator that outputs an extracted interference signal of a frequency to be extracted; and the delay means that inputs the extracted interference signal and gives a delay equivalent to the delay of the band wave generator to this input. extraction circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9714385A JPS61255146A (en) | 1985-05-08 | 1985-05-08 | Interference wave extracting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9714385A JPS61255146A (en) | 1985-05-08 | 1985-05-08 | Interference wave extracting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61255146A JPS61255146A (en) | 1986-11-12 |
| JPH044778B2 true JPH044778B2 (en) | 1992-01-29 |
Family
ID=14184346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9714385A Granted JPS61255146A (en) | 1985-05-08 | 1985-05-08 | Interference wave extracting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61255146A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2543757B2 (en) * | 1988-12-28 | 1996-10-16 | 日本無線株式会社 | Urban noise elimination circuit |
| JP2561867B2 (en) * | 1990-02-07 | 1996-12-11 | 国際電信電話株式会社 | Interference reduction device |
| US5974101A (en) * | 1992-04-28 | 1999-10-26 | Canon Kabushiki Kaisha | Spread spectrum modulation communication apparatus for narrow band interference elimination |
-
1985
- 1985-05-08 JP JP9714385A patent/JPS61255146A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61255146A (en) | 1986-11-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2004040898A3 (en) | System and method for suppressing noise in a phase-locked loop circuit | |
| KR20000023531A (en) | Sweep pilot technique for a control system that reduces distortion produced by electrical circuits | |
| JPH044778B2 (en) | ||
| US4602219A (en) | Jitter reduction circuit for frequency synthesizer | |
| JP2746152B2 (en) | Distortion compensation circuit | |
| US4023115A (en) | Means for controlling the phase or frequency output of an oscillator in a loop circuit | |
| US5272451A (en) | Clock reproducing circuit for eliminating an unnecessary spectrum | |
| JPH0335612A (en) | Fm demodulation circuit | |
| KR100550630B1 (en) | Direct digital frequency synthesized phase locked loop frequency synthesizer and its method for improving spurious characteristics | |
| JPH0525410B2 (en) | ||
| KR100738345B1 (en) | Clock Generator and Method | |
| EP0344856B1 (en) | Video signal processing circuit | |
| JPH0496428A (en) | Radio equipment | |
| JPH0774630A (en) | Digital frequency synthesizer Output signal parasitic spectral line reducer | |
| JPH0525411B2 (en) | ||
| JPH0644720B2 (en) | Interference wave extraction circuit | |
| KR950012956B1 (en) | Frequency Modulation Detection Circuit | |
| KR0120589B1 (en) | Digital noise reduction apparatus | |
| JPH02268020A (en) | phase synchronized circuit | |
| JPH0359617B2 (en) | ||
| JPS60198410A (en) | Detecting circuit for rotation signal | |
| JPH0130332B2 (en) | ||
| JPS63198406A (en) | wideband FM modulator | |
| JPS6013333B2 (en) | Phase synchronization method | |
| JPS6181027A (en) | Pll circuit |