JPH0251987A - Decoder for picture signal - Google Patents

Abstract

PURPOSE:To obtain an economical decoder by utilizing the delaying element of a predictor for two purposes of a predicting signal generation and the absorption of a phase difference. CONSTITUTION:A phase difference detector 4 detects the phase difference between a decoding signal R and an external synchronizing signal S, namely, by how many number in the number of sampling picture elements a frame synchronizing signal is shifted. The detection result is used for the modification of the read address of a memory to be ordinarily used in a predictor 3. For example, in the case of the phase difference (difference between a generation time tA of the synchronizing signal and a generation time tB of the external synchronizing signal in an encoding loop) D=tA$-tB, when D is expressed by the number of sampling picture elements, at the time of reading (x-D) address to a read address (x) of the predicting signal, an output picture signal OUT synchronizing to an external period is obtained. Thus, since a conventional frame synchronizer is not needed, the title decoder can be made economical.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a moving image signal transmission device.

C. Prior Art] Conventionally, when displaying an image decoded and reproduced on the receiving side, such as a television signal, by inputting it into an external synchronization signal as a reference signal prepared on the receiving side, the image shown in FIG. 9 has been used. It has been common practice to use a frame synchronizer 2 to which an external synchronization signal S is input after the decoding device 1 connected to the transmission path.

[Problem to be solved by the invention]

Since the frame synchronizer 2 is still expensive even today, it is not economical to add another one after the decoding device 1 as shown in FIG. 9, and it would also increase the number of devices, making it inconvenient. Met.

[Means to solve the problem]

In order to solve such problems, the image signal decoding device according to the present invention provides a decoding method that obtains a decoded signal from a predicted signal and encoded information of an image signal including synchronization supplied from a transmission path or a recording medium. means for generating a predicted signal using a decoded signal, supplying the predicted signal to the decoding means and simultaneously outputting the predicted signal after shifting the predicted signal by a specified time; and means for specifying a time to the predicted signal generating means. The predicted signal generating means is configured to detect a phase difference between an arbitrary external synchronization signal and a synchronization signal corresponding to either the decoded signal or the predicted signal.

Further, a buffer memory that matches the transmission or continuous output speed and the decoding speed, a means for decoding the encoded image signal read from the buffer memory and reproducing the image signal, and a code read from the buffer memory. means for detecting information representing synchronization included in the converted image signal; and a buffer for preventing detection of information representing synchronization from being delayed by a predetermined amount from a predetermined timing of an external synchronization signal supplied from the outside. A means for speeding up reading from the memory is provided.

[Effect]

The image signal decoding device according to the present invention does not require a conventional frame synchronizer.

〔Example〕

The invention set forth in claim 1 (hereinafter referred to as the "first invention")
An example of the invention (hereinafter referred to as "second invention") described in claim 2 will be described.

First, the operating principle of the first invention will be explained using FIG. In the figure, 3 is a predictor, 4 is a phase difference detector, and L is a transmission path. The phase difference detector 4 detects the phase difference between the decoded signal R and the external synchronization signal S, that is, detects how many sampling pixels the frame synchronization signal deviates from. This detection result is used in the predictor 3 to modify the mesori read address normally used. For example, the phase difference (generation time tA of the synchronization signal within the encoding loop)
and the generation time tll of the external synchronization signal) D = tA-1
, and if D is expressed by the number of immediately sampled pixels, then (x-D
) address, an output image signal OUT synchronized with the external period can be obtained.

In this manner, the first invention uses the delay element used to generate the predicted signal to simultaneously correct the phase difference. Therefore, when one screen is used to generate a prediction signal, it is possible to correct the phase difference of one screen at most.

−In terms of boat fishing, the amount of delay elements used to generate predicted signals (
(delay time) can be corrected. Furthermore, this amount is the same for both positive and negative phase differences. For example, in the above example, if the phase difference is negative, x-Dwx+I
Address D1 will be read. Of course, since the memory capacity is usually limited, the address following the maximum address must be regarded as the zero address.

Next, an embodiment of the image signal decoding device according to the first invention will be described with reference to FIG. In Figure 2, 1
0 is a subtracter, 11 is a quantizer, 12 is an adder, 13 is a predictor, 14 is a code converter, 20 is a code inverse converter, 21 is an adder, 22 is a predictor, 23 is an external synchronization signal generator It is a vessel.

An image signal such as a television signal supplied via the transmission kill is combined with a prediction signal supplied from the predictor 13 and the subtracter 1.
0 is subtracted, and the difference is quantized in the quantizer 11. The quantized difference, that is, the prediction error, is added to the prediction signal in an adder 12 to obtain a locally decoded signal. This locally decoded signal is supplied to the predictor 13,
Used to generate prediction signals. Here, a description will be given assuming that the predictor is an interframe predictor using delay elements for one screen. At this time, it is possible to absorb up to a maximum phase difference of one frame and draw it into the external synchronization signal. The quantized prediction error is converted into an efficient code, such as a Huffman code, in the code converter 14, matched with the transmission speed of the transmission line L2, and after forming a signal format for transmission, the code is sent to the transmission line L2. Output as data. This transmission path L2 may be a recording medium.

The coded data including the prediction error transmitted via the transmission line L2 is operated in the code inverse converter 20 in the opposite manner to the code converter 14 to obtain a prediction error signal, and the predicted signal is supplied via the transmission &%L3. and is added in an adder 21 to obtain a decoded signal. This decoded signal is transmitted! , 14 to the predictor 22. The predictor 22 generates a prediction signal by delaying the supplied decoded signal by one screen time, and at the same time matches the phase with the external synchronization signal supplied from the external synchronization signal generator 23 via the transmission line L5. Generates a signal and outputs it to the outside via transmission &i6.

Next, the operation of the predictor 22 will be described in detail with reference to FIGS. 3 and 4. The decoded signal supplied via the transmission line L4 is delayed by one screen time in the memory 221 and then taken into the latch 222. Here, for simplicity, it is assumed that there is no delay in the latch 222. The output of this latch 222 is output as a prediction signal via the transmission line L3. This one-screen delay is caused by the synchronization generator 224
A write counter 225 and a read counter 226 each controlled by a timing pulse supplied from a transmission line L7. Address information W supplied via L8,
given by R1. In other words, the address information W(!
:R1 phase difference force screen or counter 225.2
26 is reset for each screen, there is no phase difference (provided that writing to the memory 221 is performed after reading).

The phase difference between the external synchronization signal a supplied via the transmission line L5 and the timing pulse b supplied from the synchronization generator 224 is detected by the phase detector 227, and
8. Phase difference al when the phase of external synchronization signal a is al and the phase of timing pulse b is bl
When the absolute value of −bl is D (pixel), when the phase a1 is ahead of the phase b1, the arithmetic unit 228 uses R1.
- subtraction is performed, and conversely, if it is delayed, R1 + D
Perform the addition of . The image in the memory 221 is read out according to the read address modified by D, such as R1-D or R1+D, is temporarily held in the latch 223, and is output.

This operation will be supplemented with reference to FIG.

It is assumed that addresses R1, R2 (R1-D or R1+D), and W are given in this order during one cycle of the clock for one pixel (in the figure, from the rising edge of the clock of al to the next rising edge). Figure (b)).

At this time, input data for writing (FIG. 4(C)) is normally supplied in synchronization with one cycle of the clock. FIG. 4 (d+
The output data of FIG. 4 (also corresponding to address R2) is
The output data in e) is output from the memory 221 at the time when each address information is given, but latches 222 and 223 are used to correct the timing of these outputs.
is used.

In this embodiment, it is necessary to have a configuration in which reading from two different addresses and writing to one address in the memory 221 can be completed within one clock cycle, but this can be easily achieved by using high-speed memory. be.

In the above explanation, since the capacity of the memory 221 is one screen, the maximum phase difference that can be absorbed is one screen. However, if this phase difference is much smaller than one screen, for example, several lines (scanning lines), This can be combined with prediction using a delay on the order of a few lines.

Next, the operating principle of the second invention will be explained.

As shown in FIG. 5, the image signal supplied from the transmission path and encoded and expressed with a smaller amount of information than the original signal is temporarily stored in the buffer 30, and the input speed from the transmission path and the encoded image signal are The speed is matched with the decoding speed at . −
The information stored in the buffer 30 is normally sent to the decoding unit 31.
The image signal is decoded and reproduced in response to a request REQ from
must be adjusted to match.

First, Figures 5 and 6 show how the decoding device is pulled in from its initial state, such as after power-on or immediately after adding an external synchronization signal.
This will be explained with reference to the figures. First, the contents are read from the buffer 30 in response to the request REQ (step 41),
The presence or absence of a synchronization code representing a synchronization signal is checked (step 42).
), if there is none, the buffer is read empty, that is, the contents of the buffer are read out one after another (step 43),
When a synchronization code is detected, idle reading is stopped. In this state, it waits for the arrival of an external synchronization signal S indicating a predetermined timing (step 44). NOP in step 45 actually indicates a state where nothing is done. When an external synchronization signal is received, a normal decoding operation is performed (step 46), but the starting point of this operation on each screen coincides with frame synchronization in the case of a television signal, for example, and is already drawn into the external synchronization signal. This means that

Note that the above operations are unrelated to image signal encoding algorithms such as prediction methods and transform encoding.

An embodiment of the twentieth invention will be described below with reference to FIGS. 7 and 8. In addition, in FIG. 7, the case of predictive coding will be explained as an example, but even if orthogonal transformation is used or the two are combined, the wooden effect number code of the present invention will be used. There is no difference.

An image signal is inputted via the transmission line L11, and the difference between this image signal and the prediction signal supplied from the predictor 53 is calculated by the subtracter 50, and the result is supplied to the quantizer 51 as a prediction error. The quantizer 51 normally limits the number of levels that the prediction error can take, and serves to limit the amount of generated information. The quantized prediction error is supplied to an adder 52 and a variable length encoder 54. Adder 52 adds this prediction error and the prediction signal to generate a locally decoded signal and supplies it to predictor 53 . Here, the predictor 53 includes intra-frame prediction such as previous value prediction, direct prediction and separate prediction for color television signals,
There are no particular restrictions such as interframe prediction, and any of them can be used.

The variable length encoder 54 converts the output of the supplied quantizer 51 using a variable length code such as a Huffman code. The code-converted prediction error is then sent to buffer 5.
5. The buffer 55 outputs the prediction error to the transmission line L12 after matching the encoding rate and the transmission line L12.

Next, the operation on the receiving side will be explained. The buffer 60 temporarily stores the encoded image signal supplied from the transmission path L12, and reads the encoded image signal according to a request from the variable length decoder 61. This request is sent to transmission line L13.
The read image signal is transmitted through the transmission line L1
4 to a variable length decoder 61 and a controller 64. The controller 64 detects the synchronization signal in this image signal, examines the phase relationship with the external synchronization signal supplied from the external synchronization signal generator 63 via the transmission line L15, and outputs the synchronization signal from the transmission line L1.
6 to a buffer 60 and a variable length decoder 61. Details of the operation of the controller 64 will be described later.

The variable length decoder 61 restores the quantized prediction error by performing the inverse operation of variable length encoding on the transmitting side, but during this time, if decoded data is insufficient, it generates a request to add data. , requests the output from the buffer 60 via the transmission line L13.

The control signal supplied via the transmission line L16 is transmitted to the buffer 6.
When empty reading is instructed for 0, the variable length decoder 61 ignores all input data. The prediction error obtained by the variable length decoder 61 is added to the prediction signal in an adder 65 to generate a decoded signal. This decoded signal is output to the outside via the transmission line L17 and simultaneously supplied to the predictor 22 and used to generate a predicted signal.

Next, the operation of the controller 64 will be explained in detail with reference to FIGS. 6 and 8. First, the retraction in the initial state will be explained. The synchronization detector 641 is the transmission 5iL14
A synchronizing signal is detected from the output of the buffer 60 supplied through the buffer 60 (steps 41 and 42 in FIG. It is supplied to a comparator 642 and an idle reading control circuit 643 via line L18. In the state of the logic level rlJ, the idle reading command is stopped and a standby state is entered (steps 44 and 45). If a synchronization signal is received from the outside, normal decoding operation begins (step 46), but as long as the synchronization signal does not arrive, the standby state continues.

Once in a steady state, as long as there are no transmission path errors and the decoding operation continues correctly, a synchronization signal is always output from the buffer 60 before the decoding of a given screen is completed.
At this point, the device waits for an external synchronization signal.

When the steady state is broken due to a transmission path error, etc., the initial state described above begins to be drawn.

Note that when an external synchronization signal arrives, the logic level of the output of the synchronization detector 641 becomes "0". When the external synchronization signal arrives when the logic level is "0", the comparator 642 determines that normal operation is possible, and the idle read control circuit 643 instructs the buffer 60 to perform steady continuous output. Before a synchronization signal is detected for the output of the buffer 60, that is, when an external synchronization signal arrives while the logic level is rOJ, the comparator 642 transmits an abnormal state to the idle reading control circuit 643, and the air control circuit 643 instructs empty reading of the buffer 60.

Note that in order to realize the pull-in to the external synchronization signal as described above, it is necessary to appropriately select the pull-in range and buffer capacity. In reality, if the buffer capacity is set slightly larger than one screen of encoded image signals, the pull-in range is approximately 1
It becomes a screen.

In addition, although the above explanation took the predictive coding method as an example,
The second invention is not limited to a prediction method as long as it is an encoding method that reduces the amount of information of the original image and transmits it.

〔Effect of the invention〕

As explained above, the first invention uses the delay element of the predictor for the two purposes of generating a predicted signal and absorbing a phase difference at the same time, thereby eliminating the need for a frame synchronizer as in the past. Therefore, there is an effect that an economical decoding device can be obtained without increasing the number of devices.

In addition, the second invention realizes the frame synchronizer function with a simple additional circuit using a buffer memory that is always used in a normal image signal decoding device. Since the same effect can be easily obtained with this invention, the same effect as that of the first invention can be obtained. This is especially effective when pulling in external synchronization for a large number of decoding devices.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram for explaining the first invention in detail, Fig. 2 is a system diagram showing an embodiment of the first invention, and Fig. 3 is a diagram showing the principle of the first invention.
A system diagram showing the predictors that make up the device shown in the figure.
5 is a time chart for explaining the operation of the predictor shown in FIG. 5, a principle diagram for explaining the second invention in detail, and FIG.
FIG. 7 is a flowchart for explaining the second invention in detail, FIG. 7 is a system diagram showing an embodiment of the second invention, FIG. 8 is a system diagram showing a controller constituting the device of FIG. 7, FIG. 9 is a system diagram showing a conventional image signal decoding device. 10... Subtractor, 11... Quantizer, 12.21.
... Adder, 13, 22゛... Predictor, 14... Code converter, 20... Code inverse converter, 23... External synchronization signal generator.

Claims (2)

[Claims] (1) A decoding means for obtaining a decoded signal from a predicted signal and encoded information of an image signal including synchronization supplied from a transmission path or a recording medium, and a decoding means for generating a predicted signal using the decoded signal. The prediction signal generation means is equipped with a prediction signal generation means capable of simultaneously supplying the signal to the computer and simultaneously outputting the signal after being shifted by a specified time; and means for specifying the time to the prediction signal generation means; An image signal decoding device that detects a phase difference between a synchronization signal and a synchronization signal corresponding to either the decoded signal or the predicted signal. (2) a buffer memory that matches the transmission or readout speed and the decoding speed; a means for decoding the encoded image signal read from the buffer memory to reproduce the image signal; and a means for reproducing the image signal by decoding the encoded image signal read from the buffer memory; means for detecting information representing synchronization contained in an encoded image signal; and means for detecting information representing synchronization so as not to be delayed by a predetermined amount from a predetermined timing of an external synchronization signal supplied from the outside. and means for speeding up reading from the buffer memory.