JPH0448732A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0448732A
JPH0448732A JP15785990A JP15785990A JPH0448732A JP H0448732 A JPH0448732 A JP H0448732A JP 15785990 A JP15785990 A JP 15785990A JP 15785990 A JP15785990 A JP 15785990A JP H0448732 A JPH0448732 A JP H0448732A
Authority
JP
Japan
Prior art keywords
phosphorus
wiring
polysilicon film
polysilicon
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15785990A
Other languages
Japanese (ja)
Inventor
Yoshihiko Okamoto
岡本 佳彦
Mitsuhiro Tomikawa
富川 光博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15785990A priority Critical patent/JPH0448732A/en
Publication of JPH0448732A publication Critical patent/JPH0448732A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To restrain the roughening of the surface of a polysilicon and decrease the wiring short by the remains after etching or the scattering of wiring resistance by the roughness of the edge of wiring by specifying the concentration of the phosphorus, which is contained in a polysilicon film wherein phosphorus is diffused, below a specified value. CONSTITUTION:The surface of a silicon substrate 4 is thermally oxidated, and a thin silicon oxide film 3 is formed thereon, and then a polysilicon film is stacked by the chemical vapor growth method under decompression. Next, phosphorus glass is formed on the polysilicon film, and is heat-treated to diffuse phosphorus into the polysilicon film (phosphorus treatment). At this time, the concentration of phosphorus inside the polysilicon film is made 6X10<20>atm/cm<3> or less, and for the resistivity, 8X10<-4>OMEGA.cm can be gotten. For polysilicon wiring, the crystal particles are suppressed low, so there is no remains after etching nor roughening of wiring edge, thus favorable one can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多種の薄膜を積み重ねて製造される多層配線
技術を用いた半導体装置の製造方法に関し、特に電極と
して用いるポリシリコン配線の形成方法に関するもので
ある。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device using multilayer wiring technology in which various thin films are stacked and manufactured, and in particular, a method for forming polysilicon wiring used as an electrode. It is related to.

〔従来の技術〕[Conventional technology]

第2図は、例えば従来の減圧下における化学的気相成長
法により成膜したリン拡散されたポリシリコン膜を写真
製版処理後にエツチングしたリン拡散されたポリシリコ
ン配線を示すものであり、同図(a)はその平面図を、
同図(b)は同じくその断面図をそれぞれ示している。
FIG. 2 shows a phosphorus-diffused polysilicon wiring formed by etching a phosphorus-diffused polysilicon film formed by conventional chemical vapor deposition under reduced pressure after photolithography. (a) is the plan view,
The same figure (b) similarly shows the sectional view.

図において、lはポリシリコンの結晶粒、2はエツチン
グ残、3はシリコン酸化膜、4はシリコン基板である。
In the figure, 1 is a polysilicon crystal grain, 2 is an etching residue, 3 is a silicon oxide film, and 4 is a silicon substrate.

第2図に示すリン拡散されたポリシリコン配線は、まず
シリコン基板4の表面を熱酸化して薄いシリコン酸化膜
3を形成後、減圧下における化学的気相成長法によりポ
リシリコン膜を堆積する。
The phosphorus-diffused polysilicon wiring shown in FIG. 2 is produced by first thermally oxidizing the surface of a silicon substrate 4 to form a thin silicon oxide film 3, and then depositing a polysilicon film by chemical vapor deposition under reduced pressure. .

次いで、ポリシリコン膜上にリンガラス膜を形成して熱
処理を行ない、ポリシリコン膜内にリンを拡散させる(
リン処理と呼ぶ)。
Next, a phosphorus glass film is formed on the polysilicon film and heat treated to diffuse phosphorus into the polysilicon film (
(called phosphorus treatment).

このとき、ポリシリコン膜内でのリン濃度は8X l 
O” atm/cm!程度で、抵抗率は7.5X10−
4Ω・clが得られる。ところが、配線抵抗を下げるた
めにポリシリコン膜内のリンの拡散量を多くするため、
リン処理時にシリコンの結晶が大きく成長してしまう。
At this time, the phosphorus concentration within the polysilicon film is 8X l
O” atm/cm!, and the resistivity is 7.5X10-
4Ω·cl is obtained. However, in order to increase the amount of phosphorus diffused within the polysilicon film in order to lower the wiring resistance,
Silicon crystals grow large during phosphorus treatment.

その後写真製版処理を行ない、エツチングによりポリシ
リコン配線が形成される。
Thereafter, photolithography is performed and polysilicon wiring is formed by etching.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の製造方法は以上のように行なわれているので、ポ
リシリコン配線形成にあたっての写真製版処理後のエツ
チング時にシリコン結晶粒が大きいためにエツチングさ
れず残り、隣り合う配線とショートする、あるいは結晶
粒ごとエツチングされ、配線エツジがあれる。このため
、配線の場所によっては配線幅が異なることにより、配
線抵抗がばらつくという問題がある。
Conventional manufacturing methods are carried out as described above, so during etching after the photolithography process for forming polysilicon wiring, silicon crystal grains are large and remain unetched, resulting in short circuits with adjacent wiring, or crystal grains. The wiring edges are etched. Therefore, there is a problem in that the wiring resistance varies because the wiring width differs depending on the location of the wiring.

本発明は上記のような問題点を解決するためになされた
もので、リン拡散されたポリシリコン膜のシリコン結晶
粒を小さ(押さえ、エツチング残による配線ショート、
あるいは配線幅が異なることによる配線抵抗のばらつき
をなくそうとするものである。
The present invention was made to solve the above-mentioned problems, and it reduces the size of the silicon crystal grains in the phosphorus-diffused polysilicon film, suppresses wiring shorts due to etching residue,
Alternatively, it is an attempt to eliminate variations in wiring resistance due to differences in wiring width.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る半導体装置の製造方法は、リン拡散された
ポリシリコン膜の膜内に含まれるリンの濃度を6 X 
I O” atm/cm3以下と規定するものである。
In the method for manufacturing a semiconductor device according to the present invention, the concentration of phosphorus contained in the phosphorus-diffused polysilicon film is reduced to 6×
IO" atm/cm3 or less.

〔作用〕[Effect]

本発明においては、リン拡散されたポリシリコン膜の膜
内のリン濃度を6 X 10 ” ate/cs+’以
下と規定したので、このポリシリコン膜表面のあれを押
さえることができる。
In the present invention, since the phosphorus concentration in the polysilicon film into which phosphorus is diffused is defined to be 6×10” ate/cs+′ or less, roughness on the surface of the polysilicon film can be suppressed.

〔実施例〕〔Example〕

次に、本発明を第1図の実施例に基づいて説明する。 Next, the present invention will be explained based on the embodiment shown in FIG.

第1図(a)及び山)は本発明の製造方法により得られ
たポリシリコン配線の模式的な平面図およびその断面図
であり、図中同一符号は同一または相当部分を示してい
る。
1(a) and 1) are a schematic plan view and a sectional view thereof of a polysilicon wiring obtained by the manufacturing method of the present invention, and the same reference numerals in the figures indicate the same or corresponding parts.

本実施例の方法は、まずシリコン基板4の表面を熱酸化
して薄いシリコン酸化膜3を形成後、減圧下における化
学的気相成長法によりポリシリコン膜を堆積する。
In the method of this embodiment, first, the surface of a silicon substrate 4 is thermally oxidized to form a thin silicon oxide film 3, and then a polysilicon film is deposited by chemical vapor deposition under reduced pressure.

次いで、ポリシリコン膜上にリンガラス膜を形成し゛て
熱処理を行ない、ポリシリコン膜内にリンを拡散させる
(リン処理)。このとき、ポリシリコン膜内でのリン濃
度は6 X 10 ” atm/cm”以下にリン処理
されたおり、抵抗率は8 X 10−’Ω・clllが
得られる。ポリシリコン膜内のリンの拡散量を6 X 
10 ” atm/c園3以下にするため、リン処理時
のシリコンの結晶の成長の度合いが小さくなり、小さな
結晶粒となる。その後、写真製版処理を行ない、エツチ
ングにより所定パターンのポリシリコン配線を形成する
ことができる。
Next, a phosphorus glass film is formed on the polysilicon film, and heat treatment is performed to diffuse phosphorus into the polysilicon film (phosphorus treatment). At this time, the phosphorus concentration in the polysilicon film was treated with phosphorus to be less than 6 x 10 ''atm/cm'', and the resistivity was 8 x 10 -' Ω·clll. The amount of phosphorus diffused in the polysilicon film is increased by 6
10" Atm/c is less than 3, so the degree of silicon crystal growth during phosphorous treatment is reduced, resulting in small crystal grains. After that, photolithography is performed and polysilicon wiring in a predetermined pattern is formed by etching. can be formed.

このようにして形成されたポリシリコン配線は、第1図
(al及び(b)に示すように、その結晶粒が小さく押
さえられるので、エツチング残や配線エツジのあれがな
く、良好なものが得られる。
In the polysilicon wiring formed in this way, the crystal grains are suppressed to a small size, as shown in Figure 1 (al and (b)), so there is no etching residue or rough wiring edges, and good quality can be obtained. It will be done.

なお、上記実施例では、減圧下における化学的気相成長
法によりポリシリコン膜を堆積後、リン処理を行なった
が、ポリシリコン膜を堆積後、リン処理に代わってリン
をイオン注入法で6XlO” atig/c1以下注入
し、熱処理を行なっても同様の効果が得られる。
In the above example, phosphorus treatment was performed after depositing the polysilicon film by chemical vapor deposition under reduced pressure. "A similar effect can be obtained by implanting less than atig/c1 and performing heat treatment.

また、上記実施例では、減圧下における化学的気相成長
法によりリンドープのないポリシリコン膜を堆積したが
、代わりに、6 X I O” ate/cm3以下に
リンドープされたポリシリコン膜を堆積後、熱処理を行
なっても同様の効果が得られる。
Further, in the above example, a polysilicon film without phosphorus doping was deposited by chemical vapor deposition under reduced pressure, but instead, a polysilicon film doped with phosphorus to less than 6 X I O" ate/cm3 was deposited. Similar effects can be obtained by heat treatment.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、多種の薄膜を積み重ねて
製造される多層配線技術を用いた半導体装1の製造方法
において、リン拡散されたポリシリコン膜の膜内に含ま
れるリン濃度を6X10t0ate/cm3以下にした
ので、該ポリシリコン膜の表面のあれを押さえることが
できる。そのため、配線として用いた場合、後工程での
エツチング残による配線ショート、あるいは配線のエツ
ジあれによる配線抵抗のばらつきが少なくなるという効
果がある。
As described above, according to the present invention, in the method for manufacturing the semiconductor device 1 using multilayer wiring technology in which various types of thin films are stacked, the phosphorus concentration contained in the phosphorus-diffused polysilicon film is reduced to 6X10t0ate. /cm3 or less, it is possible to suppress roughness on the surface of the polysilicon film. Therefore, when used as wiring, there is an effect that variations in wiring resistance due to wiring short circuits due to etching residues in post-processes or uneven wiring edges are reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)及び(b)は本発明の一実施例による半導
体装置のシリコン基板上での配線として用いた場合の平
面図および断面図、第2図(a)及び(′b)は従来の
半導体装置のシリコン基板上での配線として用いた場合
の平面図および断面図である。 1・・・ポリシリコンの結晶粒、2・・・エツチング残
、3・・・シリコン酸化膜、4・・・シリコン基板。 代 理 人 大 石 増 雄 蕗1 凶 (b) 1;ホ0リシリコン4#&ずL 4: シリコン−4羊( 第2 図
FIGS. 1(a) and (b) are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention when used as wiring on a silicon substrate, and FIGS. 2(a) and ('b) are FIG. 2 is a plan view and a cross-sectional view of a conventional semiconductor device used as wiring on a silicon substrate. 1... Polysilicon crystal grains, 2... Etching residue, 3... Silicon oxide film, 4... Silicon substrate. Agent Masuo Oishi 1 Ko (b) 1; Holi Silicon 4#&zuL 4: Silicon-4 Sheep (Fig. 2

Claims (1)

【特許請求の範囲】[Claims]  多種の薄膜を積み重ねて製造される多層配線技術を用
いた半導体装置の製造方法において、リン拡散されたポ
リシリコン膜の膜内に含まれるリン濃度を6×10^2
^0atm/cm^3以下にすることを特徴とする半導
体装置の製造方法。
In a method for manufacturing a semiconductor device using multilayer wiring technology in which various types of thin films are stacked, the phosphorus concentration contained in the phosphorus-diffused polysilicon film is set to 6×10^2.
A method for manufacturing a semiconductor device, characterized in that it is ^0 atm/cm^3 or less.
JP15785990A 1990-06-15 1990-06-15 Manufacture of semiconductor device Pending JPH0448732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15785990A JPH0448732A (en) 1990-06-15 1990-06-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15785990A JPH0448732A (en) 1990-06-15 1990-06-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0448732A true JPH0448732A (en) 1992-02-18

Family

ID=15658945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15785990A Pending JPH0448732A (en) 1990-06-15 1990-06-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0448732A (en)

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