JPH0449457A - Direct memory access transfer control device - Google Patents

Abstract

PURPOSE:To obtain a DMA transfer control device by a simple hardware by controlling the execution cycle of direct memory access (DMA) in accordance with the specific status detection of a bus cycle. CONSTITUTION:A bus use allowable signal 45 is supplied to a timing control part 32 as a DMA execution allowable signal 46 through a DMA wait control circuit 33. When the signal 46 is activated and aquires bus using right, DMA transfer to a channel outputting the DMA request of the highest priority order out of plural DMA requests is started. Under the control of the timing control part 32 and a register selecting circuit 39, the contents of an address register 34 in an executing channel are read out in each transfer to form and output a DMA address. Data transfer is executed in accordance with a previously specified operation format. Consequently, a specific hardware such as a buffer register is not required for a register for storing various parameters.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to direct memory access (hereinafter referred to as DMA).
The present invention relates to a control device for performing high-speed data transfer between a memory and a peripheral device using a method called .

[Conventional technology]

The direct memory access method has been widely used as a high-speed data transfer method, and
A control device for performing MA transfer has become an essential part of an information processing system.

FIG. 5 is a block diagram showing an example of an information processing system including a conventional DMA transfer control device. The DMA transfer control device 4 starts operation after receiving a DMA request signal 8 from the peripheral device 6, and transmits a DMA response signal 9 to the peripheral device 6 upon starting the DMA transfer. DMA transfer involves reading data at a specified address in the memory 5 and transferring it to the peripheral device 6 via the data input/output bus 21, and transferring data from the peripheral device 6 to the memory via the bus 2. In some cases, the DMA end signal 10 is transferred to a specified address within the DMA 5 and written therein, and in either case, when the data transfer is completed, a DMA end signal 10 is supplied to the peripheral device 6. DM
When the A transfer control device 4 receives the DMA request signal 8, it sends a bus use request signal 11 to the bus control circuit 2 of the central processing unit (hereinafter referred to as CP tJ) 1. The bus control circuit 2 arbitrates bus use requests from the arithmetic processing circuit 3, refresh control device 7, etc., and returns a bus use permission signal 12 if there is no request with higher priority than the DMA transfer request. DMA transfer control device 4 is permitted to use address bus 20 and data input/output bus 21. When the DMA transfer control device 4 obtains the right to use the bus,
Data transfer is performed continuously via an address bus 20 and a data input/output bus 21. Arbitration of these bus rights takes place prior to the actual bus cycle. Also, D
The MA transfer control device 4 is equipped with a plurality of transfer paths (hereinafter referred to as channels), and selects and executes a channel according to the request source. Each channel is assigned control information such as a transfer destination address, a transfer source address, and the number of transfers. These channels are also selected prior to the actual bus cycle.

[Invention or problem to be solved]

As described above, in the conventional DMA transfer control device, the right to use the bus is switched and the corresponding channel is selected prior to the actual bus cycle. Therefore, if a bus cycle due to an access command occurs to change the control information of each channel, such as the transfer destination address or transfer source address, in the bus cycle immediately before the DMA execution cycle, the DMA
There may be a temporary conflict between the channel designation by A and the designation by the access command, causing a situation in which different channels are designated at the same time, resulting in an inconvenience. Therefore, when executing a program related to a DMA channel, do so while detecting that no DMA execution cycle will occur, or after prohibiting transfer operations, and then perform a DMA channel program in the middle of the program.
It was necessary to prevent requests from being accepted. Also,
DMA to temporarily hold control information for each channel
required special hardware such as buffer registers that were not used directly during the execution cycle.

In addition, in the conventional DMA transfer control device, once the right to use the bus is obtained, the DMA transfer control device continuously performs DMA transfer without giving up the right to use the bus.
Since the transfer was being executed, it was necessary to extend the DMA execution cycle and transfer the data to a peripheral device with a slow processing speed, and the bus was occupied by the DMA transfer for a long period of time, reducing the efficiency of bus usage. There is also the problem that it gets worse.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA transfer control device that implements a function of controlling DMA execution cycles while bus use is permitted using simple hardware.

Another object of the present invention is to provide an MA transfer control device that can significantly reduce the processing load on CPtJ and that can be designed optimally depending on the application.

[Means to solve the problem]

The DMA transfer control device of the present invention is characterized in that, in DMA transfer control after obtaining the right to use the bus, the DMA execution cycle is controlled in accordance with the detection of a specific state of the bus cycle.

The direct memory access transfer control device of the present invention includes a storage means for storing various parameters for DMA control;
a transfer control circuit that executes DMA transfer using various parameters; means that receives a valid MA transfer request and generates a bus use request signal; and suspension means that detects a specific state of a bus cycle; and means for receiving a bus use permission signal in response to a bus use request.

In the present invention, the transfer control circuit performs transfer→no cycle activation control based on the bus use permission signal and the detection of the hash cycle state.

In another aspect of the present invention, a transfer cycle is generated at every bus cycle of a plurality of bus cycles during a bus usage permission state based on a bus usage permission signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a DMA transfer control device according to an embodiment of the present invention includes a priority control unit 31 that determines priorities and arbitrates DMA transfer requests based on the determined priorities;
A timing control unit 32 that generates internal timing and controls the operation of DMA transfer, an address register 34 that stores the address of the memory to be subjected to DMA transfer for each channel (hereinafter referred to as DMA address), An address adder/subtractor 35 that updates the contents of the address register 34 of the channel being executed for each transfer, a callan 1 to register 36 that stores the number of transfers for each channel, and a callan of the channel being executed for each transfer. 1 to register 36
a DMA control register 38 that controls the operation mode of DMA transfer, etc.;
DMA way 1 that delays the start of DMA transfer execution
A control circuit 33 for reading or writing by the CPU, three register selection circuits for selecting registers to be used during transfer, and an address line 40 for supplying the DMA address, It includes an address bus 20, a data input/output bus 21, and various control lines (for 22-23 and 41-51).

The address register 34, color 1 register 36, and DMA control register 38 are all connected to the CPU via the CPU's address bus 20, three register selection circuits, a control line (for register selection signal 48), and a data input/output bus 21. , and the CPU stores the start address of the memory subject to DMA transfer in the address register 34 via these lines before executing the DMA transfer.
Then, the number of transfers is stored in the count register 36, and the operation control information is stored in the DMA control register 38, respectively. The priority control unit 31 receives a DMA request signal 41 from a peripheral device.
When a valid MA transfer request is received from a peripheral device, the timing controller 3
2 of the occurrence of a DMA request. Timing control section 3
In order to control the DMA transfer control device, address bus 20, and data input/output bus 21 (hereinafter collectively referred to as the bus) on behalf of the CPU, 2 is a bus control unit for the CPU bus control unit. A use request signal 44 is sent. The bus control unit arbitrates the right to use the bus, and returns a bus use permission signal 45 if there is no request with a higher priority due to a bus use request due to DMA transfer. The bus use permission signal 45 is sent to the DMA way 1 via the control circuit 33.
The MA execution permission signal 46 is supplied to the timing control unit 32. I) When the MA execution permission signal 46 is activated and the right to use the lotus is acquired, DMA transfer is started for the channel with the highest priority among the DMA requests.

In the DMA execution cycle, 1) Under the control of the timing control unit 32 and the register selection circuit 39, the contents of the address register 34 of the channel being executed are read for each transfer, a DMA address is generated, and the DMA address is Output via line 40. Also, the address adder/subtracter 35 performs an operation, and by not writing back to the address register 34 again, the DMA
Update your address.

(2) The number of transfers is controlled by reading the content of the count register 36, decrementing it with the count subtractor 37, and writing it back to the count register 36.

(3) For the peripheral device requesting DMA transfer,
DMA response signal 4 indicating that it is an MA execution cycle
Returns 2.

The above steps (1) to (3) are repeated to perform data transfer according to a prespecified operation mode. When the count register 36 and count subtractor 37 count a predetermined number of transfers, a DMA end detection signal 47 is generated. When the timing control unit 32 detects the DMA end detection signal 47, it activates the DMA end signal 43 and notifies the peripheral device requesting the DMA transfer of the end of a series of data transfers by DMA.

Here, the DMA weight control circuit 33 will be explained in detail using FIG. 2. FIG. 2 is a logic circuit diagram of the DMA weight control circuit 33. The DMA weight control circuit 33 of this embodiment includes an address decoder 100, an OR gate 101, AND gates 102, 103, and 105, and a latch circuit 104. Address decoder 100 decodes the address on address bus 20 of the CPU and detects that the address assigned to address register 34 and count register 36 has been output. The OR gate 101 receives a signal 2 indicating that the CPU is in a read operation.
2 and a signal 23 indicating that a write operation is in progress, it generates a signal indicating that a read or write operation has been performed. AND gate 102 is address decoder 1
00 output, the output of the OR gate Lot, and the bus use request signal 44 are input, and the CPU reads or writes to the address register 34 and the count register 36 during a bus use request by DMA transfer. Generates a signal indicating. The output of AND gate 102 is input to latch circuit #1104. The AND gate 103 inputs the basic clock signal 50 for internal operation and the end period signal 51 of the bus cycle, and generates a signal indicating the switching timing of the right to use the bus. The latch circuit 104 receives the output of the AND gate 102, and receives the output of the AND gate 103.

The AND gate 105 outputs the state of the input signal during a period of 1'', that is, at the timing of switching the right to use the bus.
The inverted signal of the output of the latch circuit 104 and the bus use permission signal 45 are input, and a DMA execution permission signal 46 is generated. The DMA execution permission signal 46 is transmitted to the timing control section 32.
is supplied to

Next, regarding the operation of the DMA wait control circuit 33, the third
The explanation will be made with reference to the operation timing diagram of the DMA weight control circuit 33 shown in the figure. In the bus cycle (A), when the CPU reads or writes the address register 34 or the count register 36, the output of the address decoder 100 and the output of the OR gate 101 both become 1°.At this time, the DMA When a request to use the bus due to transfer (signal 44) is generated, the output of the AND gate 102 becomes "°1'".At gate 102
The output of latch circuit 104 is input to latch circuit 104.
The output of 04 is the bus signal from T3 of bus cycle (A).
The period at T2t of cycle (B) is "1". On the other hand, the bus use permission signal 45 is determined at the bus use right switching timing, because the bus cycle for reading or writing by the CPU ends. It becomes 11111 from T3 of bus cycle (A).Latch circuit 1
The output of 04 is inverted and input to the AND gate 105, and the output of the AND gate 105, that is, the DMA execution permission signal 46, is input from T3 to 1 of the bus cycle (B).
''. When the DMA execution permission signal 46 becomes °°1°', the DMA execution cycle starts from the bus cycle (C).

In this way, in this embodiment, it is determined that the address register 34 or the count register 36 is accessed by the CPU during a request to use the bus due to DMA transfer, and if the access is performed, the bus is After an interval of one bus cycle, the DMA execution permission signal 46 is activated. In this way, the DMA execution cycle is not started immediately following the CPU access, so the address register 3
4 or the count register 36 can be read and written normally in a stable state.

In addition, in this embodiment, wait control for reading and writing of the address register 34 and current register 36 has been explained, and the same control can be easily realized for the DMA control register 38 etc. without being restricted by address allocation. It goes without saying that it can be done.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 4, parts and signals that are equivalent to those in the embodiment of FIG. 1 are indicated using the same numbers. The frequency dividing circuit 60 in this embodiment receives the bus use permission signal 45, the basic clock signal 50, and the bus cycle end period signal 51, and divides the bus cycle period by four. That is, a valid bus cycle is generated only once in four bus cycles while the bus is in the enabled state. The output of the frequency dividing circuit 60 is
The timing control unit 32 uses the DMA execution permission signal 46 as the DMA execution permission signal 46.
is supplied to Therefore, in a state where the use of the bus is permitted, the DMA execution permission signal 46 is activated for one bus cycle every four bus cycles, and the DMA execution permission signal 46 is activated at regular intervals.
A transfer cycles occur periodically.

As described above, in the second embodiment, a bus cycle for DMA transfer occurs only once every four hash cycles during the period in which use of the bus for DMA transfer is permitted. Therefore, it is possible to easily transfer data at an optimal speed to a peripheral device with slow processing speed. In this embodiment, frequency division by four has been described, but it goes without saying that other frequency divisions can be implemented without being restricted by the frequency division ratio.

〔Effect of the invention〕

As explained above, according to the present invention, in DMA transfer control after obtaining the right to use the bus, the following is achieved by controlling the DMA execution cycle in accordance with the detection of a specific state of the bus cycle. It's effective.

(1) When programming a DMA channel, there is no need to detect the occurrence of a DMA execution cycle or to prohibit DMA transfer operations, which greatly reduces the burden on software processing and improves overall device performance. Performance can be significantly improved.

(2) Since special hardware such as a buffer register is not required for registers that store various parameters for DMA transfer control, hardware can be reduced and optimal design can be achieved.

(3) Even for peripheral devices with low processing speeds, the total data processing can be optimized so that data can be transferred easily at the optimum speed without deteriorating the efficiency of use of the lotus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the DMA transfer control device of the present invention, FIG. 2 is a logic circuit diagram of a DMA weight control circuit in the embodiment of FIG. 1, and FIG.
FIG. 4 is a block configuration diagram showing another embodiment of the present invention, and FIG. 5 is a diagram of the operation timing of the weight control circuit.
FIG. 1 is a block configuration diagram of an information processing system including an MA transfer control device. DESCRIPTION OF SYMBOLS 1... CPU, 2... Bus control circuit, 3... Arithmetic processing circuit, 4... DMA transfer control device, 5... Memory, 6... Peripheral device, 7... Refresh control device, 84]...DMA request signal, 9,42...DMA
Response signal, 10, 4.3... DMA end signal, 11.
．． 1444... Bus use request signal, 12.45...
・Bus use permission signal, 13.40...DMA address line, ]5...Refresh address line, 2
0...Address bus, 2]...Data input/output bus, 22...Signal indicating that reading operation is in progress, 23...Signal indicating that writing operation is in progress, 31...Priority control section ,
32... Timing control unit, 33... DMA wait control circuit, 34... Address register, 35...
・Atregi adder/subtractor, 36...Count register, 3
7... Count subtractor, 38... DMA control register, 39... Register selection circuit, 46... DMA execution permission signal, 47... I) MA end detection signal, 48...
・Register selection signals, 4...operation timing signals,
5o... Basic clock signal, 51... Bus cycle end period signal, 60... Frequency divider circuit, 100... Address decoder, 101... OR gate, 102,1
．． 03105...AND gate, 104...Latch circuit.

Claims (1)

[Claims] 1. A direct memory access transfer control device that transfers data at a specified address in a memory using a direct memory access method, comprising: a storage means for storing various parameters for direct memory access control; , direct memory using the various parameters mentioned above.
a transfer control circuit for executing access transfer; means for receiving a valid direct memory access transfer request and generating a bus use request signal; detection means for detecting a specific state of a bus cycle; and use of the bus. A direct memory access transfer control device comprising: means for receiving a bus use permission signal in response to a request signal. 2. The transfer control circuit according to claim 1, wherein the transfer control circuit performs activation control of the transfer cycle based on the bus use permission signal and the detection result of the means for detecting a specific state of the bus cycle. Direct memory access transfer controller. 3. Multiple bus accesses during the occurrence of the bus use permission signal.
2. The direct memory access transfer control device according to claim 1, wherein the transfer cycle activation control is performed by generating one valid bus cycle among the cycles.