JPH0449596A - Memory circuit - Google Patents

Abstract

PURPOSE:To directly take out the output of each memory cell by arranging I<2>L gates in accordance with each of floating gate type PROM cell transistors, and controlling a circuit to be controlled by the output of the I<2>L gate. CONSTITUTION:The outputs (drain) of the memory cells 11, 12 by floating gate type MOS transistors are connected to the inputs of the I<2>L gate 21, 22 respectively. The outputs of the gates control one ends of resistors R1, R2 so as either to open them or earth them through internal terminals 31, 32. Since voltage obtained by subtracting the VBE of a transistor 41 from VBIAS is impressed to the other ends of the resistors R1,R2, the currents of 0, alpha(VBIAS - VBE)/R1, alpha(VBIAS - VBE) . R2, alpha(VBIAS - VBE)/((1/R1) + (1/R2)) can be obtained as IOUT at the collector of the transistor 41 according to the state of ON/OFF of the I<2>L gates 21, 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit, and more particularly to a circuit that efficiently extracts the outputs of memory cells that can be written at least once in parallel.

[Conventional technology]

PROMs using floating gate MOS transistors are commercially available as memories that can be written at least once, and are useful for storing programs and data for computers and the like.

On the other hand, in recent years, adjustment and trimming of analog LSI characteristics,
A method and a bus format in which analog and digital function selection, etc. are controlled by a microcomputer in a set via a bus have been proposed and are being put into practical use.

FIG. 3 is a block diagram of a circuit that performs such conventional adjustment and trimming function selection, in which the memory cell 1 is an EEPROM or EPROM LSI, the readout circuit 2 is a microcomputer, and the circuit is connected to the bus of the microcomputer. Latch circuit 3. A controlled circuit connected to each output of this latch circuit is prepared.

Here, the controlled circuit 4 may be a logic gate for selecting a function, an analog switch for switching an analog signal, or a transistor switch for changing a resistance value.

These control signals correspond to the output signals of the latch circuit.

Currently, examples in which each block in Figure 3 is configured with separate LSIs are widely known, but there are few examples in which they are realized with a single-chip LSI, but an example of this is our company's (NEC) EPROM correction type D/A converter. In this case, an on-chip EPROM is prepared as the memory cell 1, a shift register is prepared as the readout circuit 2, and after calculating the output, it is latched by the latch circuit 3, and the MOS analog switch as the controlled circuit 4 is controlled. It is configured to output a voltage according to the voltage at the connection point of the switch.

[Problem to be solved by the invention]

In the conventional configuration described above, the memory can only be read serially in bits or words, and the stress relief control side must handle several signals simultaneously in parallel, which requires a corresponding latch circuit. 3 was required. In addition, a serial-to-parallel conversion means for passing data from the memory to the latch is essential, and a circuit for controlling the operation of sequentially reading out the required amount of data from the memory and a predetermined time period for this operation are essential.

For this reason, the device size becomes large and expensive, and the readout is performed sequentially, resulting in a lack of high speed.

However, if a conventional sense amplifier for reading is provided for each memory cell, parallel output type memory like this can be realized, but the sense amplifier occupies a large chip size, making it impractical. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit which solves the above-mentioned drawbacks, allows the output of each memory cell to be taken out directly without multiple access, and eliminates the need for readout circuits, latch circuits, etc.

[Means to solve the problem]

The structure of the memory circuit of the present invention is such that each of the floating gate type PROM cell transistors has an IL
The device is characterized in that gates are arranged, the collectors of the cell transistors are connected to the inputs of the IL gates, and the controlled circuit is controlled from the output number of the IL gates.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a memory circuit according to a first embodiment of the present invention.

In FIG. 1, the memory circuit of this embodiment has a first I
L (Integrated Injection)
Logic) game) 21.22, resistors R1 and R2,
It includes an Hpn type transistor 41, floating gate type memory cells 11 and 12, a constant current source I INJI, and a constant voltage source Vref + VBIAS. Here, the IL gate 21 includes pnp type transistors 21a, n
It has a pn type transistor 21b, and the IL gate 22 is
pnp type transistor 22a, npn type transistor 2
2b.

In FIG. 1, only the portions necessary for the memory read operation of this embodiment are depicted. Floating gate type MO8)
Memory cells 11.12 by transistors have their outputs (
trains) are each connected to an input of an IL gate 21,22. The output controls whether one end of the resistor R1 and R2 is opened or grounded via internal terminals 31 and 32. Memory cells 11 and 12 are not written to.
In general EPROMs, the threshold voltage is low when it is written ("1"), and it is high when it is written ("1").
, since it is an EEPROM, by applying a voltage in the middle of 1 = 6 to the gate as V rat, the cell at °“0”) is turned on without writing.
Cells with writing (“1”) are turned OFF. In reality, there may be an intermediate value between 0N10FF due to threshold voltage fluctuations, write characteristics, etc., so a sense amplifier is required. Therefore, the IL gate 2 is placed as an active load on the drains of the memory cells 11 and 12.
1.22 internal equivalent pnp) transistors 21a, 21
A constant current source with b is connected, and its output voltage is IL
Comparison is made using the threshold voltage (approximately 0.7V) of the gate equivalent npn) transistors 21b and 22b. In this way, the IL gate can be used as a sense amplifier with sufficient amplification. This IL gate 21, 22
The output of the transistor 41 directly controls whether or not current flows through the resistors R, , R2, and the other end of the resistor R, , R is connected to the transistor 41 from VBIAS. (approximately 0.7V) is applied, so 0N10 of IL gate 21.22 is applied.
0°a (VBIAS V
BE) / R1rα(V BIAS V Bri/R
2, α(VBIAS9 VBE) ((1/ Rt
) + (1/R2)) is available in the collector of transistor 41 as I out. Here, α is the current amplification factor (approximately 1) of the transistor 41, and I
NJI provides the injector current of the IL gate.

FIG. 2 is a circuit diagram showing a memory circuit according to a second embodiment of the present invention. In FIG. 2, the memory circuit of this embodiment is
1. L gates 21, 22, 23.24, floating gate type memory cells 11.12, 13.14,
Word switch 51.52 and bit switch 61.6
2, constant voltage source V DD+ Vref, and constant current source I
INJII I INJ2 and a pulse Vpp application line. Here, the IL gate 21 is pn
P-type transistor, npn-type transistor, output terminal 3
1. Other IL gates 22, 23, 24
also have similar transistors, and further have output terminals 32, 33, and 34, respectively.

In the embodiment shown in FIG. 2, memory cells 11 to 11 similar to those shown in FIG.
14 and IL gates 21 to 24 are arranged in a matrix, and a write circuit is added.

When reading, set the bit switches 61 and 62 to V rat
By setting the word switches 51 and 52 to the ground side and setting the word switches 51 and 52 to the ground (GND) side, a circuit equivalent to that shown in FIG. 1 is obtained, and the output of all bits can be obtained at the internal terminals 31 to 34 at the same time.

For example, when writing data to the memory cell 14, only the bit switch 62 is switched to the VPP side, and the
When writing "1", a high potential is applied, and when writing "On", GND is applied. - On the other hand, the word switch 52 applies the write VDD potential, and the other word switches 51 are turned off. When set in this manner, a write current (avalanche current) flows between the control gate of the selected memory cell 14 and the train via the base and emitter of the transistor 24b to perform a write operation. Regarding the other memory cells 11 to 13, either the write pulse is not applied to their gates or the write current path is broken, and no writing is performed. As described above, a memory circuit capable of selective writing and parallel output was obtained.

Note that the switches 51, 52, 61, and 62 can be realized by transfer gates using MOS transistors, and can be controlled by decoding the input address signal with a bit decoder and a word decoder (not shown) like in a normal memory. In addition, memory cells 11 to 14 have one P
It can be made in a single region, and separate element isolation is not required. Similarly, IL gates with a common emitter (for example, 21 and 2
2) can be created within one N region, so there is no need for separate element isolation, and this N region itself becomes a word line and can be led to the word switches 51 and 52, so there is no need to bother. No wiring area for word lines is required. Similarly, the injectors in one N region can be connected through the P expansion diffusion layer, so no wiring region is required for the injector lines. Also, memory cell 11
It is also possible to wire the gates 1 to 14 using polysilicon that constitutes the gates, and by doing so, the output lines 31 to 34 from each cell can be easily drawn out using empty space. It is possible.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to create a PROM circuit capable of serial writing and parallel output in a small area by saving the element isolation area and wiring using a diffusion layer. This has the advantage that it can be manufactured in a smaller area than when a readout circuit and a latch circuit are added to a serial readout type PROM circuit.

Note that manufacturing the PROM and the IL gate together can be realized by a derivative process that adds a floating gate or the like to the conventional B1-CMOS process.

Further, the floating gate type memory cell may be an infrared erasable EPROM or an electrically erasable EEPR or OM. It may be something like MNOS.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a memory circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional memory circuit. It is a diagram. 11-14...Floating gate type memory cell,
21-24-I L gate, 21a-24a...equivalent pnp transistor, 21b-24b...equivalent n
pn type transistor, 31-34...internal output terminal,
41...Transistor.

Claims (1)

[Claims] 1. An I^2L gate is arranged corresponding to each floating gate type PROM cell transistor, and the collector of the cell transistor is connected to the input of the I^2L gate, and the I^2L gate is connected to the input of the I^2L gate. A memory circuit characterized in that a controlled circuit is controlled by the output of a 2L gate. 2. The memory circuit according to claim 1, wherein the I^2L gate comprises an npn type and a pnp type transistor. 3. The memory circuit according to claim 1, wherein the gate of the cell transistor is provided with a signal changeover switch.