JPH0449675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0449675A JPH0449675A JP2160189A JP16018990A JPH0449675A JP H0449675 A JPH0449675 A JP H0449675A JP 2160189 A JP2160189 A JP 2160189A JP 16018990 A JP16018990 A JP 16018990A JP H0449675 A JPH0449675 A JP H0449675A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- peripheral circuit
- oxide film
- wiring
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 230000002093 peripheral effect Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、浮遊ゲート型不揮発性半導
体記憶装置（ＦＲＯＭ）を含む半導体装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a floating gate nonvolatile semiconductor memory device (FROM).
従来技術によるＰＲＯＭメモリセルを含む半導体装置に
ついて、製造工程順に第３図（ａ）〜（ｈ）を参照して
説明する。A semiconductor device including a PROM memory cell according to the prior art will be described in the order of manufacturing steps with reference to FIGS. 3(a) to 3(h).
はじめに第３図（ａ）の平面図とそのＡ−Ｂ断面図であ
る第３図（ｂ）に示すように、半導体基７板１に素子分
離用のフィールド酸化膜１０が形成され、周辺回路部（
ゲート領域９と配線領域８）を除いたメモリセル部６の
みに、第１の酸化膜２と第１のポリシリコンからなる浮
遊ゲート３ａとが形成されている。First, as shown in the plan view of FIG. 3(a) and FIG. 3(b), which is a sectional view taken along the line A-B, a field oxide film 10 for element isolation is formed on the semiconductor substrate 7, and the peripheral circuit Department (
A floating gate 3a made of first oxide film 2 and first polysilicon is formed only in memory cell portion 6 excluding gate region 9 and wiring region 8).
つぎに第３図（ｃ）の平面図とそのＡ−Ｂ断面図である
第３図（ｄ）に示すように、第２の酸化膜４と第２のポ
リシリコンらとが堆積される。Next, as shown in the plan view of FIG. 3(c) and FIG. 3(d), which is a sectional view taken along the line A-B, a second oxide film 4, second polysilicon, etc. are deposited.
つぎに第１のレジストアをマスクとして選択エツチング
され、ポリシリコン５からなるメモリセル部６の制御ゲ
ート５ａが形成される。Next, selective etching is performed using the first resist as a mask to form control gates 5a of memory cell portion 6 made of polysilicon 5.
つぎに第３図（ｅ）の平面図とそのＡ−Ｂ断面図である
第３図（ｆ）に示すように、第２のレジスト１１をマス
クとして選択エツチングされ、のこりの周辺回路部のゲ
ート電極を含む配線５ｂが形成される。Next, as shown in the plan view of FIG. 3(e) and FIG. 3(f), which is a sectional view taken along the line A-B, the second resist 11 is selectively etched using the second resist 11 as a mask, and the remaining peripheral circuit gates are etched. Wiring 5b including electrodes is formed.
このとき周辺回路部のソース−ドレイン（図示せず）が
露出されるので、ポリシリコン５の選択エツチング時の
表面損傷による特性劣化を防ぐため、メモリセル部のポ
リシリコンと周辺回り部のポリシリコンとが２度に分け
て別々にエツチングされている。At this time, the source and drain (not shown) of the peripheral circuit area are exposed, so in order to prevent characteristic deterioration due to surface damage during selective etching of the polysilicon 5, etching the polysilicon of the memory cell area and the polysilicon of the peripheral area. and are etched separately in two parts.
つぎに第３図（ｇ）の平面図とそのＡ−Ｂ断面図である
第３図（ｈ）に示すように、さらに眉間絶縁膜１２を形
成し、上層配線１３を形成してメモリセル部６の制御ゲ
ート５ａと周辺回路部の配線５ｂとを電気的に接続して
いた。Next, as shown in the plan view of FIG. 3(g) and FIG. 3(h), which is a sectional view taken along the line A-B, an insulating film 12 between the eyebrows is further formed, an upper layer wiring 13 is formed, and the memory cell portion is formed. The control gate 5a of No. 6 and the wiring 5b of the peripheral circuit section were electrically connected.
半導体装置の高速化、高集積化のため、ポリシリコンの
配線幅が狭くなって抵抗値が高くなり、遅延時間が増大
する。As semiconductor devices become faster and more highly integrated, the width of polysilicon wiring becomes narrower, the resistance value becomes higher, and the delay time increases.
そこで抵抗値を下げるために第１のポリシリコンからな
る浮遊ゲートと第２のポリシリコンからなる制御ゲート
とを厚くすると、浮遊ゲートと制御ゲートとが重なって
いるメモリセル部の周囲で段差が大きくなり、第２のポ
リシリコンからなる配線が断線してしまうという欠点が
あった。Therefore, if the floating gate made of the first polysilicon and the control gate made of the second polysilicon are made thicker in order to lower the resistance value, the difference in level becomes large around the memory cell area where the floating gate and the control gate overlap. Therefore, there was a drawback that the wiring made of the second polysilicon was disconnected.
またメモリセル部のポリシリコンと周辺回路部のポリシ
リコンとを別々に選択エツチングして形成していた。Further, the polysilicon in the memory cell portion and the polysilicon in the peripheral circuit portion are selectively etched separately.
メモリセル部のポリシリコンと周辺回路部のポリシリコ
ンとを接続する場合、パターンずれのため直接接続する
ことができないので、眉間絶縁膜と上層配線とを追加形
成して接続しなければならなかった。When connecting polysilicon in the memory cell area and polysilicon in the peripheral circuit area, direct connection is not possible due to pattern misalignment, so it was necessary to additionally form an insulating film between the eyebrows and an upper layer wiring for connection. .
本発明のＦＲＯＭメモリセルを含む半導体装置は、２層
ポリシリコンにより浮遊ゲートと制御ゲートとを含む配
線が形成されているメモリセル部以外の周辺回路部にお
いて、２層ポリシリコンが絶縁膜を介することなく直接
積層されて制御ゲートを含む配線が形成されているもの
である。In the semiconductor device including the FROM memory cell of the present invention, in the peripheral circuit area other than the memory cell area where the wiring including the floating gate and the control gate is formed of the two-layer polysilicon, the two-layer polysilicon is formed with an insulating film interposed therebetween. The interconnects including the control gates are formed by directly stacking the layers without any interference.
本発明の第１の実施例について、第１図（ａ）〜（ｄ）
を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (d)
Explain with reference to.
はじめに第１図（ａ）の平面図とそのＡ−Ｂ断面図であ
る第１図（ｂ）に示すように、半導体基板１に素子分離
用のフィールド酸化膜１０を形成し、第１の酸化膜２を
堆積し、第１のポリシリコン３を堆積して選択エツチン
グして浮遊ゲート３ａを形成する。First, as shown in the plan view of FIG. 1(a) and FIG. 1(b), which is a sectional view taken along the line A-B, a field oxide film 10 for element isolation is formed on a semiconductor substrate 1, and a first oxide A film 2 is deposited, and a first polysilicon 3 is deposited and selectively etched to form a floating gate 3a.
つぎに第１図（ｃ）の平面図とそのＡ−Ｂ断面図である
第１図（ｄ）に示すように、第２の酸化膜４を形成し、
周辺回路部の第２の酸化膜４を選択エツチングして、第
２のポリシリコン５を堆積し、制御ゲート５ａ、配線５
ｂを形成する。Next, as shown in the plan view of FIG. 1(c) and FIG. 1(d), which is a sectional view taken along the line A-B, a second oxide film 4 is formed.
The second oxide film 4 in the peripheral circuit area is selectively etched and a second polysilicon 5 is deposited to form the control gate 5a and wiring 5.
form b.
こうして周辺回路部のポリシリコンの層抵抗（ρ、）が
従来４０Ω／口であったのに対して、本実施例では第１
のポリシリコンと第２のポリシリコンとが積層されて並
列接続されているため、２５Ω／口まで低減することが
できた。In this way, the layer resistance (ρ, ) of the polysilicon in the peripheral circuit section was conventionally 40 Ω/hole, but in this example, the
Since the polysilicon layer and the second polysilicon layer are stacked and connected in parallel, the resistance can be reduced to 25 Ω/hole.
さらにメモリセル部６と周辺回路部とを、第２のポリシ
リコン５からなる配線で直接接続できるようになった。Furthermore, it is now possible to directly connect the memory cell section 6 and the peripheral circuit section with the wiring made of the second polysilicon 5.
つぎに本発明の第２の実施例について、第２図（ａ）〜
（ｄ）を参照して説明する。Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (d).
はじめに第２図（ａ）の平面図とそのＡ−Ｂ断面図であ
る第２図（ｂ）に示すように、半導体基板１に素子分離
用のフィールド酸化膜１０を形成し、第１の酸化膜２を
堆積し、第１のポリシリコン３を堆積して選択エツチン
グすることにより、周辺回路部の高抵抗素子部のポリシ
リコン３を除去する。First, as shown in the plan view of FIG. 2(a) and FIG. 2(b), which is a sectional view taken along the line A-B, a field oxide film 10 for element isolation is formed on a semiconductor substrate 1, and a first oxide A film 2 is deposited, a first polysilicon 3 is deposited, and selectively etched to remove the polysilicon 3 in the high resistance element part of the peripheral circuit part.
つぎに第２図（Ｃ）の平面図とそのＡ−Ｂ断面図である
第２図（ｄ）に示すように、第２の酸化膜４を形成し、
周辺回路部の第２の酸化膜４を選択エツチングして、第
２のポリシリコンを堆積し、制御ゲート５ａ、高抵抗素
子５Ｃを形成する。Next, as shown in the plan view of FIG. 2(C) and FIG. 2(d), which is a cross-sectional view taken along the line A-B, a second oxide film 4 is formed.
Second oxide film 4 in the peripheral circuit area is selectively etched and second polysilicon is deposited to form control gate 5a and high resistance element 5C.
この場合は高抵抗素子部分が第２のポリシリコンのみで
構成されるため、第１のポリシリコンと第２のポリシリ
コンとが直接積層されている第１の実施例と違って、第
２のポリシリコンのみで占有面積の小さい高抵抗素子を
形成することができ、しかも配線における本発明の効果
を生かすことができる。In this case, since the high-resistance element portion is composed only of the second polysilicon, unlike the first embodiment in which the first polysilicon and the second polysilicon are directly laminated, the second polysilicon is A high resistance element occupying a small area can be formed using only polysilicon, and the effects of the present invention can be utilized in wiring.
周辺回路部で第１のポリシリコンと第２のポリシリコン
とが直接積層した制御ゲートを含む配線を形成すること
により、配線抵抗を下げることができた。By forming a wiring including a control gate in which the first polysilicon and the second polysilicon are directly laminated in the peripheral circuit section, the wiring resistance can be lowered.
さらにメモリセル部の第２のポリシリコンと周辺回路部
の第１、第２のポリシリコンとを同時に選択エツチング
することにより、メモリセル部の第２のポリシリコンか
らなる配線と周辺回路部の第１、第２のポリシリコンと
を直接接続することが可能になった。Furthermore, by selectively etching the second polysilicon in the memory cell area and the first and second polysilicon in the peripheral circuit area at the same time, the wiring made of the second polysilicon in the memory cell area and the first and second polysilicon in the peripheral circuit area are etched. 1. It became possible to connect directly to the second polysilicon.
１・・・半導体基板、２・・・第１の酸化膜、３・・・
第１のポリシリコン、３ａ・・・浮遊ゲート、４・・・
第２の酸化膜、５・・・第２のポリシリコン、５ａ・・
・制御ゲート、５ｂ・・・配線、５ｃ・・・高抵抗素子
、６・・・メモリセル部、７・・・第１のレジスト、８
・・・配線領域、９・・・ゲート領域、１０・・・フィ
ールド酸化膜、１１・・・第２のレジスト、１２・・・
層間絶縁膜、１３・・・上層配線。DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First oxide film, 3...
First polysilicon, 3a... floating gate, 4...
Second oxide film, 5... Second polysilicon, 5a...
- Control gate, 5b... Wiring, 5c... High resistance element, 6... Memory cell portion, 7... First resist, 8
... Wiring region, 9... Gate region, 10... Field oxide film, 11... Second resist, 12...
Interlayer insulating film, 13... upper layer wiring.
Claims (1)
制御ゲートとを含む配線が形成されている浮遊ゲート型
不揮発性半導体記憶装置を含む半導体装置において、周
辺回路部では前記２層ポリシリコンが絶縁膜を介するこ
となく直接積層されて制御ゲートを含む配線を形成して
いることを特徴とする半導体装置。In a semiconductor device including a floating gate type nonvolatile semiconductor memory device in which a wiring including a floating gate and a control gate made of two-layer polysilicon is formed in a memory cell part, the two-layer polysilicon is an insulating film in a peripheral circuit part. 1. A semiconductor device characterized in that wiring including a control gate is formed by directly stacking layers without intervening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160189A JPH0449675A (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160189A JPH0449675A (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0449675A true JPH0449675A (en) | 1992-02-19 |
Family
ID=15709747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2160189A Pending JPH0449675A (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0449675A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0892430A1 (en) * | 1997-07-16 | 1999-01-20 | STMicroelectronics S.r.l. | Process for manufacturing an integrated circuit comprising an array of memory cells |
-
1990
- 1990-06-19 JP JP2160189A patent/JPH0449675A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0892430A1 (en) * | 1997-07-16 | 1999-01-20 | STMicroelectronics S.r.l. | Process for manufacturing an integrated circuit comprising an array of memory cells |
| US5976933A (en) * | 1997-07-16 | 1999-11-02 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing an integrated circuit comprising an array of memory cells |
| US6353243B1 (en) | 1997-07-16 | 2002-03-05 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing an integrated circuit comprising an array of memory cells |
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