JPH0449831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an imaging device that can effectively suppress pluming.

(Prior art) As previously shown in Japanese Patent Application Laid-Open No. 138371/1983
In order to prevent pluming in solid-state image sensors such as CCDs, it has been proposed to use surface recombination to eliminate excess carriers instead of providing an overflow drain on the light-receiving surface.

This method has advantages such as high sensitivity because it does not sacrifice the aperture ratio within the light-receiving surface, and horizontal resolution can be increased because the degree of integration can be improved.

1 to 3 are diagrams for explaining a blooming prevention method using such surface recombination, and FIG. 1 is a front view of a general frame transfer type CCD.

In the figure, reference numeral 1 denotes a light receiving section, which is composed of a plurality of photosensitive vertical transfer registers.

Further, reference numeral 2 denotes a storage section, which is composed of a plurality of vertical transfer registers that are shielded from light.

Reference numeral 3 denotes a horizontal transfer register, which inputs the information in each vertical transfer register of the storage section 2 by shifting one bit at the same time to the horizontal transfer register, and then transfers the video signal from the output amplifier 4 by causing the register 3 to perform a horizontal transfer operation. can be obtained.

Generally, the information formed in each vertical transfer register of the light receiving section 1 is vertically transferred to the storage section 2 during the vertical blanking period in the standard television system, and is sequentially transferred from the horizontal transfer register 3 within the next vertical scanning period. It is read line by line.

Here, it is assumed that the light receiving section 1, the storage section 2, and the horizontal transfer register 3 are each driven in two phases, and the respective transfer electrodes are _P1 , _P2 , _P3 , _P4 , _P5 , _P6 , The transfer clocks are (φp ₁ , φp ₂ ), (φp ₃ , φp ₄ ), (φp ₅
，
φp ₆ ).

FIG. 2 is a diagram showing the potential profile under such transfer electrodes P ₁ to P ₆ . For example, by applying a low level voltage -V ₁ to the electrodes P ₂ , P ₄ , P ₆ and applying the voltage to the electrodes P ₁ , P ₃ , P _{5 .} When a high-level voltage V ₂ is applied to , a potential as shown by the solid line in the figure is formed. Also, electrode
Apply low level voltage V ₁ to P ₁ , P ₃ , P ₅ and
When a high level voltage V ₂ is applied to P ₂ , P ₄ , and P ₆ , a potential as shown by the broken line in the figure is formed.

Therefore, by applying alternating voltages with opposite phases to electrodes P ₁ , P ₃ , P ₅ and electrodes P ₂ , P ₄ , P ₆ , carriers are sequentially transferred in one direction (rightward in the figure). .

In addition, the dashed-dotted line in the figure indicates a large positive voltage V ₃ at the electrode.
This shows the potential when .

FIG. 3 is a diagram showing the shape of the electrode voltage and internal potential in the thickness direction of the semiconductor substrate 6. As shown in the figure, for electrode voltage _V3 , the potential well becomes shallow and excess carrier A second state occurs in which it recombines with majority carriers at the interface with the insulating layer.

On the other hand, when the electrode voltage is _-V1 , the first state is an accumulation state, and a large number of carriers tend to gather around the interface, and the large number of carriers are supplied from, for example, a channel stopper region (not shown).

Therefore, for example, when a barrier is formed by applying a voltage -V ₁ to the electrode P ₂ , by alternately applying voltages -V ₁ and V ₃ to the voltage P ₁ , the electrode
The decimal carrier accumulated in _P1 is controlled to be below a predetermined amount.

However, image sensors using such charge recombination have the disadvantage that a clock signal for recombination is mixed into the output signal, resulting in noise.

(Objective) It is an object of the present invention to provide an imaging device that can overcome the drawbacks of the prior art.

In particular, the object is to provide an imaging device with a low nozzle and low power consumption.

(Example) The present invention will be explained below based on Examples.

FIG. 4 is a diagram showing an example of an imaging device using an imaging element according to the present invention. In this embodiment, a case of a frame transfer type CCD using a single-phase drive method will be explained.

In the figures, the same reference numerals as in FIGS. 1 to 3 indicate the same elements.

The UOD is an overflow device for discharging excess charge, which is provided on the opposite side of the light receiving section 1 to the storage section 2.
The drain is biased with a constant positive voltage V _OD .

In this embodiment, together with the transfer clock φ _PI to the light receiving section,
A clock φ _AB is applied to cause excess charge to recombine with holes at the surface recombination center and disappear.

Further, transfer clocks φ _PS and φ _S are applied to the storage section 2 and the horizontal transfer register 3, respectively.

CKD uses these clock pulses φ _PI , φ _AB , φ _PS ,
_CKG is a clock generator that generates timing signals to form these pulses, PAP is a process amplifier, and ECD is an encoder. , the video signal via the amplifier PAP is converted to NTSC by this encoder, for example.
The signal is converted to a standard television signal, such as a standard television signal.

MS is a mode setting circuit for switching the output state of various pulses by the clock driver CKD, and can switch the frequency of the recombination clock _φAB . Also, the mode setting circuit is an analog gate AG
control opening and closing.

RCC is a recording device. SW1 is a switch for forming and recording a still signal as an instruction means, and when this switch is turned on, it automatically sets the mode setting circuit to the still mode as described later, and controls the driver CKD. Gate AG is opened for one field or one frame period at the set timing.

FIG. 5 is a diagram schematically showing the electrode structure and potential in a cross section of the boundary region between the light receiving section 1 and the storage section 2. As shown in FIG.

In the figure, P _PI is the transfer electrode that applies the transfer clock φ _PI of the light receiving section, P _AB is the recombination control electrode as a recombination means for applying the recombination clock φ _AB , and P _PS is the transfer clock φ of the storage section. Transfer electrode for applying _PS , 6
E constitutes the overflow drain
n ⁺ region.

The solid line in the figure shows the potential state when low level voltages are applied as φ _PI and φ _PS , and the high level voltage is applied as φ _AB . The broken line shows the potential state when φ _PI and φ _PS are at high level and φ _AB This is the case when is set to low level.

Incidentally, a potential staircase as shown in the figure is formed in the substrate 6 by ion implantation. In addition, although not shown in the lower part of the insulating layer that is not covered by the electrodes P _PI , P _PS , and P _AB , that is, the boundary between the insulating layer and the semiconductor substrate, there is a layer for forming a virtual electrode. For example, a P-type inversion layer is formed.

Therefore, the potential in the semiconductor region not covered by the electrodes is not changed by the bias applied to each electrode.

FIG. 6 is a diagram showing an example of an electrode pattern in the region shown in FIG.

CS is a channel stop and prevents horizontal charge movement.

According to the embodiments shown in the fourth to sixth figures, the width of the electrode _PAB for charge recombination can be made sufficiently smaller than the width of the transfer electrode _PPI , so that the removal efficiency can be increased when removing excess charges.

Furthermore, in a single-phase drive type CCD image sensor, the charge recombination operation can be performed independently of the transfer operation.

Furthermore, the recombination control structure of the image sensor of this embodiment can be formed using the same process as the channel stop, including the step of forming a polysilicon gate for charge and the step of ion implantation for forming internal potential steps. .

Next, FIG. 7 shows the clock pulses φ _AB , φ _PI , φ _PS , φ _S output from the clock driver CKD to drive the image pickup block shown in FIG. 4 when the switch SW ₁ is OFF, that is, in the movie shooting mode. and a waveform diagram of the output V _OUT of the amplifier 4, etc.

A vertical blanking signal V _BLK is output between times t ₁ to _{t 3} and t ₄ to t ₆ in synchronization with the vertical synchronization signal V _D obtained for each television field.

Further, H _BLK is a horizontal blanking signal. First, during the accumulation period from time t ₁ , t ₃ to _{t 4} , and t ₆ , the level of φ _PI is set to approximately the intermediate level between −V ₁ and V ₂ .
V Fixed at ₅ level. Further, at the end of each accumulation period, whether to raise or lower φ _PI is switched for each field.

To explain this, during the accumulation period, φ _PI is reduced to V ₅
As shown in FIG. 8a, potential wells A and C are formed in the substrate under the transfer electrode _PPI and in the substrate under the virtual electrode, respectively, and electrodes are accumulated in the respective wells.

Since a plurality of pulses φ _AB are supplied during each horizontal blanking period of this accumulation period as shown in Fig. 7, the potential below the electrode P _AB goes up and down as shown in Fig. 8a. Among the charges in the well B generated when the potential is lowered, the excess charges collected near the insulating layer 5 are recombined with holes when the potential is increased, so they disappear and do not leak into the well A.

Next, by supplying a plurality of pulses of φ _AB from time t ₁ to _{t 2} and from t ₄ to _{t 5} , excess charge immediately before vertical transfer is removed.

Further, between times _t2 to _t3 and _t5 to _t6, clocks φ _PI and φ _PS of the same number as the number of pixels in the vertical direction of the light receiving section 1 and the storage section 2 are supplied in phase.

As a result, the charge in each pixel cell in the light receiving section 1 is transferred and accumulated in the corresponding storage cell in the storage section.

At this time, in the present invention, the clock φ _AB applied to the recombination electrode P _AB is fixed at _V4 .

This voltage _V4 is, for example, a voltage value such that the potential level below the electrode _PAB is located between the upper and lower limits of the potential level of the virtual electrode portion, as shown in FIG.

As described above, at the end of each accumulation period, whether to raise or lower φ _PI is switched for each field.

That is, the amounts of charge entering wells A and C (or B) during the accumulation period of the first field up to time t ₁ in FIG. 7 are respectively A _1NT , B 1NT , and B _1NT as shown in FIG. 8a.
C _1NT . Next, during vertical transfer starting from time _t2 in Fig. 7, as shown in Fig. 8b, by raising φ _PI from the intermediate level _V5 to the _V2 level at the beginning of the transfer, ',', and... The charges accumulated in the parts are added and transferred to the accumulation part. or,
The second field is set by lowering φ _PI from the intermediate level V ₅ to −V ₁ at the beginning of the transfer′,
Add the charges accumulated in and ′, and ′….

Interlacing and operation are performed by changing the combination of charges added for each field in this way.

With this configuration, it is possible to create an interlacing effect with a small number of pixels, and the dark current level does not change from field to field, making flickering less likely to occur.

When the vertical transfer is completed, the charges in the storage section are read out line by line in synchronization with the horizontal cycle by the clocks φ _PS and φ _S between times t ₃ - _{t 4} and t ₆ , and the horizontal line signal is is output as This period t ₂ ~ t ₃ , t ₆ ~
corresponds to the vertical scanning period of a standard television signal.

Next, FIG. 10 is a timing chart when switch SW1 is turned on to perform still mode photography. Switch SW1 at any time t ₀
When turned ON, the setting circuit MS outputs the MODEφ signal for the still mode, which will be described later, in synchronization with the next falling edge of the vertical blanking pulse V _BLK (time t ₃ ) and the next falling edge (time t ₆ ). .

This MODEφ signal is held until the rising time t ₄ and t ₁₁ of the next vertical blanking pulse V _BLK , respectively.

While MODEφ is output from time t ₃ to time _{t 4} , a high-speed pulse of the clock cycle is constantly supplied to φ _AB .

Moreover, while the MODEφ signal is output from time t ₆ to _{t 11} , φ _AB is at the potential V ₃ and φ _PI is at the potential V ₂
Fixed. Also, during this time, analog gate AG
It becomes ON.

The other pulses are the same as in FIG. 7.

Therefore, recombination reaches its maximum capacity while one field is read out by the pulses φ _PS and φ _S after the switch SW1 is turned on, and no pluming occurs in the image formed by the light receiving section 1 during this period.

However, since the signals read out during this time are overlapped by the nozzles, vertical stripes appear on the screen, but since the time is 1/60 seconds, they can be almost ignored.

In addition, the image signal formed in this way
Read out by pulses φ _PS and φ _S from t ₆ to _{t 11} ,
During this time, the gate AG is open, so the information is recorded on the recording device RCC.

As described above, in this embodiment, the recombination ability performed during image formation in the still mode is enhanced compared to the recombination ability performed during image formation in the movie mode, so that the image quality of still images is improved. Further, noise during image reading in this movie mode can be reduced.

Furthermore, in the movie mode, φ _AB is supplied only during the horizontal blanking period, so noise during reading does not appear on the screen.

In this embodiment, the number of pulses of φ _AB during the image forming time is controlled in order to control the recombination ability of φ _AB . For example, the P-P value (prominence value) of φ _AB may be controlled. It's okay.

That is, during image formation in still mode, φ _AB
The P-P value of φ AB may be made large, and in the case of movie mode, the P-P value of φ _AB may be made small.

In addition, in this embodiment, in the movie mode, φ _AB is supplied during the horizontal blanking period in order to reduce the number of pulses of φ _AB during the image forming period and eliminate the nozzle being read out. It is also possible to supply φ _AB of a lower frequency than in the still mode over almost the entire period of the image forming time.

The recombination ability according to the present invention is such that P of φ _AB
-Including those based on P value, frequency, etc.

During this period, especially from time t ₆ to _{time t 11} , φ _AB is at a constant level, so that no noise occurs while reading the signal V _OUT , and power consumption can also be saved.

Also, during this period (t ₆ to t ₁₁ ), the potential barrier in the light receiving section 1 is lower than the barrier in the storage section 2 for most of the time. That is, in FIG. 5, the potential of region X is as shown by the broken line,
Since the potential of region Y is as shown by the solid line, even if φ _AB is not operating, almost no overflowed charge leaks into the storage section.

Furthermore, since the overflow drain is provided on the opposite side of the light receiving section 1 from the storage section 2, the overflowing charge in the light receiving section 1 is discharged to the power supply _VOD .

Note that the potential of area X in the storage section is lowered by the horizontal blanking period due to pulse φ _PS ;
Since the effective image signal (the image signal formed up to time _t1 ) moves downward in the storage section 2 in _FIG . The charge introduced can be ignored.

Next, we will explain the configuration example of the clock driver CKD.
1 and its timing chart is shown in FIG. 12. In Figures 11 and 12, _φD is a pulse that occurs twice in one horizontal period, and TRG is a frame transfer trigger pulse for frame transfer, which is generally output during the vertical blanking period or related timing. be done.

Also, this pulse TRG is disclosed in, for example, Japanese Patent Application No. 58-61098.
As shown in the above, the output may be output at any timing other than the vertical blanking period. In that case, the image accumulation time is
It can also be controlled by the timing of TRG.

Also, D ₁ ~ _{D 5} are D flip-flops, OR ₁ ~
OR ₄ is an OR gate, CNT is a counter, SG is φ _PI ,
Pulse generation circuit that forms φ _PS , SW ₂ to _{SW 5} are analog switches, DIV ₁ and DIV ₂ are 1/2 frequency dividers, A
1 to A9 are AND gates, and NOR1 is a NOR gate.

Since the D flip-flop D1 uses the pulse TRG as a clock and the input D is always at a high level, the output T1 becomes a high level when triggered by TRG (time _t7 ).

Therefore, due to the D flip-flops D2 and D3, the clock is delayed by φD2 (at time t ₃ ).
2 occurs, which clears D1 and T
1 is a low level. The length of this high level section of T1 can be decreased or increased by increasing or decreasing the number of D flip-flops. In this example, this interval t ₇ ~
t ₆ is one horizontal period, but if D ₂ is abbreviated, it is 1/2H
section. After _T2 becomes high level, the output _T3 of D flip-flop D4 becomes high level at time _t9 , and after a predetermined clock, the output CARRY of counter CNT causes flip-flops D3 and D4 to become high level.
is cleared (time t ₁₀ ), T2 and T3 become low level, and the frame transfer ends.

Since φ _PI , φ _PS, etc. can be generated in the φ _PI , φ _PS generating circuit SG as shown in FIG. 7, they are not particularly shown here.

Horizontal blanking signal H _BLK is AND gate A1
The output of the AND gate A1 is logically summed with T1 in the OR gate OR2 to become T4.

Therefore, T4 is the horizontal blanking period excluding the vertical transfer period _t8 to _t10 , and the output T of the part immediately before the output T2.
The signal is at a high level during one of the high level periods _t7 to _t8 .

The clock signal CLK, the divided signals of the frequency dividers DIV1 and DIV2, and the output of the mode setting circuit MS are ANDed.
It is supplied to gates A2 to A5, and the following relationship holds true.

That is, the output SEL1 from the mode setting circuit MS=
When H, SELφ=H (hereinafter referred to as MODE3),
The clock is used as the output T5 of the OR gate OR3.
CLK is output as is, SEL1=H, SELφ=
When in L (hereinafter referred to as MODE2), T5 is a clock.
CLK1/2 frequency divided output.

Also, when SEL1=L and SELφ=H (hereinafter referred to as MODE1), T5 becomes a 1/4 frequency divided output of the clock CLK, and when SEL=L and SELφ=L (hereinafter referred to as MODEφ), A5 is always at the H level. becomes.

Note that T1 is a timing pulse for supplying φ _AB immediately before vertical transfer, and supplies φ _AB while at a high level.

Further, T3 is a timing pulse for vertical transfer, and vertical transfer by φ _PI and φ _PS is performed while at a high level.

In addition, during the movie mode when the fourth illustrated switch SW1 is OFF, the cycle of φ _AB is determined according to the mode MODE1 to MODE3 selected by the mode setting circuit.
φ _AB is supplied at the timing shown in FIG.

Also, φ _PI and φ _PS are output from the generation circuit SG.
The timing of these pulses is as shown in FIG.

Also, once the switch SW1 is turned ON, the output of the vertical scanning period circuit MS immediately after becomes MODEφ, so SEL1=L, SELφ=L, and the output T
7 is a high level.

Flip-flop D5 operates at the rising edge of T7, and assuming that the initial state is Q=L and =H, the output Q of D5 remains at a high level until the next rising edge of T7, time _t6 . Therefore, between times _t3 and _t4 , AND gate A7 outputs a high level and A8 outputs a low level.

On the other hand, between times _t6 and _t11 , AND gate A7 outputs a low level and A8 outputs a high level. While gate A7 is at high level, AND gate A9 guides clock signal CLK to OR gate OR4, so that while clock CLK is at high level, the switch is disabled.
SW3 is closed and φ _AB = +V ₃ , and while clock CLK is at low level, switch SW5 is closed and φ _AB = -V ₁
becomes.

Note that the NOR gate NOR1 is open when _T2 is not at a high level. While T2 is at a high level, switch SW4 is closed and φ _AB =+V ₄ is fixed. or,
Since φ _AB is supplied at high speed during the high level period of T1 immediately before T2 becomes high level, smearing and blooming can be prevented. Further, since the AND gate A8 is at a high level from time _t6 to time _t11 , the switch SW3 is closed during this period, and _φAB becomes the potential _V3 .
Also, during this time, the analog switch SW2 is switched to the b side, and φ _PI is fixed at the potential +V ₂ .

As explained above, in this embodiment, the pulse φ _AB is supplied for a predetermined period just before the frame transmission period, and the excess charge immediately before the transfer is canceled, so that smearing or blooming does not occur.

Also, when recording one field or only one field of video output from the image sensor, φ _AB is constantly supplied in large numbers at high speed during a predetermined image forming period, and φ _AB is kept constant while recording the formed image. Since it is held at a potential, it saves power and does not introduce noise. Furthermore, blooming can be stably removed during image formation. In addition, while reading out the image formed by the light receiving section, the potential barrier inside the light receiving section is set to be lower than the potential barrier inside the storage section most of the time, so that the pluming image taken during signal readout is not the same as the readout signal from the storage section. It's not as good as that.

Furthermore, since the overflow drain is provided on the side of the light receiving section opposite to the storage section, overflow charges between this drain can be quickly removed.

In the above explanation, an example of a frame transfer type CCD using a single-phase drive method has been described, but it goes without saying that the present invention is similarly applicable to a CCD image sensor using a multi-phase drive method. or,
It is clear that the present invention is applicable not only to CCDs but also to all types of image sensors that convert image signals into charges and store them. Further, although this embodiment is configured to record images for one field period in still mode, it goes without saying that it is also applicable to a system that forms and records images for two fields. Also, in this example
During MODEφ, φ _PI = V ₂ and φ _AB = V ₃ , but
Even if φ _PI =V ₅ and φ _AB =V ₄ , the same effect can be obtained since the barrier is lower than the barrier in the storage section. Further, in this embodiment, the signals SEL1, SEL1,
Since the potential level of not only φ _AB but also φ _PI can be controlled by SELφ, the number of input pins of the clock driver can be reduced.

(Effects) According to the present invention, blooming of still images can be stably prevented because the recombination ability during the image formation period is enhanced, and when a movie image is formed, the recombination ability during the image formation period is improved. Since the capacity is lowered, the number of nozzles for reading can be reduced.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of a conventional CCD image sensor, Figure 2 is a diagram explaining the driving method of the sensor shown in Figure 1, Figure 3 is a diagram explaining the principle of surface charge recombination, and Figure 4 is a diagram of the present invention. 5 is a schematic cross-sectional view showing an example of the structure of an image sensor suitable for the image sensor of the present invention; FIG. 6 is a diagram showing an example of the electrode pattern of the element shown in FIG. FIG. 7 is a drive timing chart of the imaging device of the present invention in movie mode, FIGS. 8a and 8b are diagrams explaining the potential states at predetermined timings in the same mode, and FIG. 9 is a diagram showing the potential under the electrode P _AB . 10 is a timing chart in still mode, FIG. 11 is a diagram showing an example of the configuration of a clock driver, and FIG. 12 is a partial timing chart thereof. 1... Light receiving section, 2... Accumulating section, P _AB ... Recombination control electrode as recombination means, CKD... Clock driver as control means, SW1... Switch as instruction means.

Claims (1)

[Scope of Claims] 1. A light receiving section that converts an optical image into a charge signal, and applying a recombination control signal to the light receiving section for recombining a part of the charge of the light receiving section with charges of other polarity. an instructing means for instructing switching between a still mode in which the light receiving section forms an image signal for one screen and a movie mode in which the image signal for multiple screens is formed; In accordance with the instruction output, the amount of charge that can be recombined in the light receiving section during image formation in the still mode is made to be larger than the amount of charge that can be recombined in the light receiving section during image formation in the movie mode. and a control means for applying a recombination control signal to the recombination electrode.