JPH0451146U - - Google Patents
Info
- Publication number
- JPH0451146U JPH0451146U JP1990092683U JP9268390U JPH0451146U JP H0451146 U JPH0451146 U JP H0451146U JP 1990092683 U JP1990092683 U JP 1990092683U JP 9268390 U JP9268390 U JP 9268390U JP H0451146 U JPH0451146 U JP H0451146U
- Authority
- JP
- Japan
- Prior art keywords
- cap
- semiconductor device
- lid body
- semiconductor
- directions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Description
第１図はこの考案の半導体装置の一実施例の断
面図、第２図は従来のＥＰＲＯＭの実装構造の一
部断面斜視図である。 １……プリント基板、２……チツプ搭載部、３
……端子、４……ペースト、５……半導体素子、
６……金属細線、７……チツプ保護樹脂、８……
キヤツプ、９……放熱体。
面図、第２図は従来のＥＰＲＯＭの実装構造の一
部断面斜視図である。 １……プリント基板、２……チツプ搭載部、３
……端子、４……ペースト、５……半導体素子、
６……金属細線、７……チツプ保護樹脂、８……
キヤツプ、９……放熱体。
Claims (1)
- 【実用新案登録請求の範囲】 (1) (a) キヤツプ内に包囲された半導体素子と
、 (b) この半導体素子の主表面と、上記キヤツ
プの上部内周面に接触するように、ポツテイング
により形成され、この半導体素子の発熱を上記キ
ヤツプに伝達するフイラを含有したチツプ保護樹
脂と、 (c) 上記キヤツプの外周面に設けられ、上記
チツプ保護樹脂を介して伝達された上記半導体素
子の熱を放熱する放熱体と、 よりなる半導体装置。 (2) キヤツプは、金属、セラミツク、樹脂のい
ずれかで形成されることを特徴とする請求項１記
載の半導体装置。 (3) キヤツプは、四方向の側面部から成る蓋体
、２方向の側面部からなる蓋体、四本柱やぐら状
の蓋体、のいずれかの形状を有することを特徴と
する請求項１記載の半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990092683U JPH0451146U (ja) | 1990-09-05 | 1990-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990092683U JPH0451146U (ja) | 1990-09-05 | 1990-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451146U true JPH0451146U (ja) | 1992-04-30 |
Family
ID=31829334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990092683U Pending JPH0451146U (ja) | 1990-09-05 | 1990-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451146U (ja) |
-
1990
- 1990-09-05 JP JP1990092683U patent/JPH0451146U/ja active Pending