JPH0451183U - - Google Patents
Info
- Publication number
- JPH0451183U JPH0451183U JP9309990U JP9309990U JPH0451183U JP H0451183 U JPH0451183 U JP H0451183U JP 9309990 U JP9309990 U JP 9309990U JP 9309990 U JP9309990 U JP 9309990U JP H0451183 U JPH0451183 U JP H0451183U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- group
- transfer
- switch
- switch contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Mounting Components In General For Electric Apparatus (AREA)
Description
第1図は本考案による一実施例のスイツチ装置
の外観構造を示す斜視図、第2図は実施例の平面
図、第3図は実施例の回路図、第4図は従来例を
説明するための回路図、第5図は従来例における
電子回路基板の実装例を示す平面図である。
符号の説明;5……スイツチ装置、6……筐体
、7a〜7h……スイツチ接点、8a〜8p……
リード端子、9a〜9h……バツフア回路、10
a,10b……バツフア、11,12,14,1
5……論理和回路、13,16……インバータ回
路。
Fig. 1 is a perspective view showing the external structure of a switch device according to an embodiment of the present invention, Fig. 2 is a plan view of the embodiment, Fig. 3 is a circuit diagram of the embodiment, and Fig. 4 explains a conventional example. FIG. 5 is a plan view showing an example of mounting an electronic circuit board in a conventional example. Explanation of symbols: 5... Switch device, 6... Housing, 7a to 7h... Switch contact, 8a to 8p...
Lead terminal, 9a to 9h...Buffer circuit, 10
a, 10b...Batsuhua, 11, 12, 14, 1
5...OR circuit, 13, 16...inverter circuit.
Claims (1)
のオン・オフ切換えに応じた電圧レベルの信号を
各スイツチ接点の出力側接点に発生させる抵抗群
と、これらの出力接点に発生する信号を電力増幅
して転送するバツフア回路群と、これらのバツフ
ア回路群の信号転送と非転送の切換え制御を行う
制御回路とを、集積回路素子の標準規格に適合す
るピツチ間隔のリード端子群を一体に備えるパツ
ケージ内に内蔵し、 且つ該パツケージの一側に上記スイツチ接点を
一体に形成すると共に、電源供給端子、グランド
端子、上記バツフア回路の出力信号を出力するた
めの出力端子、上記制御回路に制御指示信号を印
加するための入力端子を上記リード端子群で構成
したことを特徴とするスイツチ装置。[Claim for Utility Model Registration] A plurality of switch contacts, a group of resistors that generate a signal at the output side of each switch contact at a voltage level corresponding to the on/off switching of these switch contacts, and a group of resistors that generate a signal at the output side of each switch contact, A group of buffer circuits that power amplify and transfer the generated signals and a control circuit that controls switching between signal transfer and non-transfer of these buffer circuit groups are connected to lead terminals with pitch spacing that conforms to the standard specifications for integrated circuit devices. A power supply terminal, a ground terminal, an output terminal for outputting the output signal of the buffer circuit, and the switch contact are integrally formed on one side of the package. A switch device characterized in that an input terminal for applying a control instruction signal to a control circuit is constituted by the group of lead terminals described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9309990U JPH0451183U (en) | 1990-09-06 | 1990-09-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9309990U JPH0451183U (en) | 1990-09-06 | 1990-09-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451183U true JPH0451183U (en) | 1992-04-30 |
Family
ID=31830054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9309990U Pending JPH0451183U (en) | 1990-09-06 | 1990-09-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451183U (en) |
-
1990
- 1990-09-06 JP JP9309990U patent/JPH0451183U/ja active Pending
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