JPH0459958U - - Google Patents

Info

Publication number
JPH0459958U
JPH0459958U JP1990102305U JP10230590U JPH0459958U JP H0459958 U JPH0459958 U JP H0459958U JP 1990102305 U JP1990102305 U JP 1990102305U JP 10230590 U JP10230590 U JP 10230590U JP H0459958 U JPH0459958 U JP H0459958U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
voltage
output
stabilization control
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990102305U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990102305U priority Critical patent/JPH0459958U/ja
Publication of JPH0459958U publication Critical patent/JPH0459958U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Continuous-Control Power Sources That Use Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係る電源アレイの一実施例を
示す平面図、第２図は第１図の電源アレイの回路
構成図、第３図は本考案の他の実施例を示す平面
図である。 １，２……電源安定化制御用半導体ペレツト、
３……基板、４，５……入力端子、６……入力用
リード、７，８……出力端子、９，１０……出力
用リード。 FIG. 1 is a plan view showing one embodiment of the power supply array according to the present invention, FIG. 2 is a circuit diagram of the power supply array shown in FIG. 1, and FIG. 3 is a plan view showing another embodiment of the present invention. be. 1, 2...Semiconductor pellet for power supply stabilization control,
3... Board, 4, 5... Input terminal, 6... Input lead, 7, 8... Output terminal, 9, 10... Output lead.

Claims (1)

【実用新案登録請求の範囲】 (1) 単一のパツケージ内で、単一の基板上に複
数の電圧安定化制御用半導体ペレツトをマウント
し、各半導体ペレツトの入力端子を単一の入力用
リードに共通接続し、各出力端子を異なる出力用
リードにそれぞれ接続したことを特徴とする電源
アレイ。 (2) 入力用リードと電圧安定化制御用半導体ペ
レツトの入力端子の接続部に、電圧降下用半導体
ペレツトを介挿したことを特徴とする請求の項(1
)記載の電源アレイ。 (3) 電圧降下用半導体ペレツトが、この半導体
ペレツトに接続された電圧安定化制御用半導体ペ
レツトの出力電圧と入力端子電圧の中間電圧を出
力する電圧安定化制御用半導体ペレツトの出力に
よつて制御されることを特徴とする請求の項(2)
記載の電源アレイ。[Claims for Utility Model Registration] (1) Within a single package, multiple semiconductor pellets for voltage stabilization control are mounted on a single substrate, and the input terminals of each semiconductor pellet are connected to a single input lead. A power supply array characterized in that a common connection is made between the two output terminals, and each output terminal is connected to a different output lead. (2) Claim (1) characterized in that a semiconductor pellet for voltage drop is inserted between the input terminal of the input lead and the semiconductor pellet for voltage stabilization control.
) described power supply array. (3) The voltage drop semiconductor pellet is controlled by the output of the voltage stabilization control semiconductor pellet that outputs an intermediate voltage between the output voltage of the voltage stabilization control semiconductor pellet connected to this semiconductor pellet and the input terminal voltage. Claim (2) characterized in that
Power array as described.
JP1990102305U 1990-09-29 1990-09-29 Pending JPH0459958U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990102305U JPH0459958U (en) 1990-09-29 1990-09-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990102305U JPH0459958U (en) 1990-09-29 1990-09-29

Publications (1)

Publication Number Publication Date
JPH0459958U true JPH0459958U (en) 1992-05-22

Family

ID=31846433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990102305U Pending JPH0459958U (en) 1990-09-29 1990-09-29

Country Status (1)

Country Link
JP (1) JPH0459958U (en)

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