JPH0451485Y2 - - Google Patents
Info
- Publication number
- JPH0451485Y2 JPH0451485Y2 JP1988063301U JP6330188U JPH0451485Y2 JP H0451485 Y2 JPH0451485 Y2 JP H0451485Y2 JP 1988063301 U JP1988063301 U JP 1988063301U JP 6330188 U JP6330188 U JP 6330188U JP H0451485 Y2 JPH0451485 Y2 JP H0451485Y2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- semiconductor
- rounded
- width
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Die Bonding (AREA)
Description
〔産業上の利用分野〕
本考案は、半導体素子を気密封止する半導体パ
ツケージ用のセラミツク基板の改良に関するもの
である。
〔従来の技術〕
高密度集積回路(IC)を含む半導体素子は、
酸化、汚染等の外気環境に非常に影響され易く、
このため外気環境の如何より性能劣化又は信頼性
の低下を招来し易い。そこでこれを防止する為に
プラツチツク、金属又はセラミツク基板で形成し
たパツケージにより半導体素子を気密封止するこ
とが行なわれており、なかでも特に厳しい使用条
件を要求されるものは、長期的に安定した気密封
止状態が得られるセラミツク基板のパツケージに
よつている。
従来のこの種のセラミツク基板においては、コ
ーナーに丸味がつけられ、またエツジにはセラミ
ツク基板の外周に沿つて微少な段差を1つ有し、
かつ丸味を施した二つの稜部を形成して、セラミ
ツク基板に生ずる欠けや亀裂の発生を防止してい
る(例えば、特公昭57−450062号及び第4図)。
〔考案が解決しようとする課題〕
半導体パツケージに用いられるセラミツク基板
は、一般に金属酸化物をプレス成形し、高温焼結
シテ形成したものが多く、耐薬品性、耐熱性、良
好な電気絶縁性並びに高い熱伝導性を有する。そ
の反面、耐衝撃性、機械的強度が比較的弱く、こ
のため、半導体素子の組立て工程中及び製品運搬
中に於ける半導体パツケージ相互の衝突時によ
り、特にパツケージ外周端面のコーナー、エツジ
に欠けや亀裂を生ずる事が多く、信頼性の低下、
ひいては商品性の損失をまねいていた。
従来の半導体パツケージ用のセラミツク基板に
あつては、単に直方体でかつ平板状に形成された
ものに比べると、セラミツク基板に生ずる欠けや
亀裂をある程度防止出来るものの、この欠けや亀
裂を所定以下の大きさにおさえることができず、
かかる意味で製品の歩留りがわるい欠点があつ
た。
本考案は、従来技術の有するこのような問題点
に鑑みてなされたものであり、その目的とすると
ころは、半導体素子の組立て工程中並びに製品運
搬中に於いてセラミツク基板のエツジやコーナー
に欠けや亀裂の発生が極めて少なく、又発生した
場合でも欠けや亀裂の大きさが極めて小さいた
め、製品の歩留りが非常に良好であるセラミツク
基板を提供しようとするものである。
〔課題を解決するための手段〕
上記目的を達成するために、本考案におけるセ
ラミツク基板は、半導体素子を収容するキヤビテ
イ部を有し、その外周端面のコーナーに微少な丸
味が施されている半導体パツケージ用のセラミツ
ク基板であつて、前記キヤビテイ部が穿設された
面と反対側の端面におけるエツジに、前記セラミ
ツク基板の外周に沿つて、微少な段差を有する2
つの段部と丸味を施した3つの稜部を形成し、し
かも前記2つの段部を、上方側の第1の段部の幅
L1と、下方側の第2部の幅L2とをL1≫L2の関係
に形成してなるものである。
〔実施例〕
実施例について図面を参照して説明する。
第1図〜第3図において、半導体パツケージ用
のセラミツク基板1は、巾2cm、長さ5cm、厚み
1.5mmのほど直方体の平板状に形成されており、
その長手方向の一端面(側面)には、半径約1mm
の半円形の自動挿入用ノツチ部2が形成されてい
る。又このセラミツク基板1の外周端面のコーナ
ー3には、それぞれ、半径約0.4mm程度の丸味が
つけられているとともに、半導体素子Aを収容す
るためのキヤビテイー部4の穿設された面と反対
側の面の端面におけるエツジ5には、前記セラミ
ツク基板1の外周に沿つて、各々が約0.1mm程度
の微小な段差を有する2つの段部6,7と半径
0.04〜0.06mm程度の丸味を施した3つの稜部8,
9,10が形成され、しかも上方側の第1の段部
6の幅L1と下方側の第2の段部7の幅L2とをL1
≫L2の関係に形成してある(第3図参照)。符号
1Aはセラミツク基板で構成されたキヤツプを、
1Bは該キヤツプ1Aと同形のベースを示す。1
1はキヤツプ1Aとベース1Bとを接着し、かつ
パツケージ内を気密封止する封じガラスである。
又12はリードフレームである。
以上のように構成されたセラミツク基板1は、
半導体パツケージの組立工程や、組み立てられた
半導体パツケージの運搬工程等において、セラミ
ツク基板1同志がランダムに衝突しても、コーナ
ー3は丸味がつけられているため、コーナー3に
加えられた衝撃力は緩和され、したがつてコーナ
ー3に欠け、亀裂は発生し難くなつており、ま
た、エツジ5は、丸味をつけられたつの稜部8,
9,10によつて2つの段部6,7をもつて形成
されているため、エツジ5に加えられた衝撃力は
3つの稜部8,9,10に分散されるとともに緩
和されるので、エツジ5にも、欠け、亀裂は発生
し難くなつている。
そして、以上の実施例において説明したセラミ
ツク基板を用いて組み立てた半導体パツケージに
ついて衝撃試験を行なつたところテーブル1のよ
うな試験結果が得られた。
[Industrial Application Field] The present invention relates to an improvement of a ceramic substrate for a semiconductor package that hermetically seals a semiconductor element. [Prior Art] Semiconductor devices including high-density integrated circuits (ICs)
It is highly susceptible to external environment such as oxidation and pollution,
For this reason, performance deterioration or reliability is likely to deteriorate depending on the outside air environment. To prevent this, semiconductor devices are hermetically sealed using packages made of plastic, metal, or ceramic substrates. It relies on a ceramic substrate package that provides an airtight seal. In conventional ceramic substrates of this type, the corners are rounded and the edges have one minute step along the outer periphery of the ceramic substrate.
In addition, two rounded edges are formed to prevent chipping and cracking from occurring in the ceramic substrate (for example, Japanese Patent Publication No. 57-450062 and FIG. 4). [Problem to be solved by the invention] Ceramic substrates used in semiconductor packages are generally made by press-molding metal oxides and forming high-temperature sintered sheets, and they have good chemical resistance, heat resistance, good electrical insulation, and Has high thermal conductivity. On the other hand, their impact resistance and mechanical strength are relatively low, and as a result, when semiconductor packages collide with each other during the assembly process of semiconductor elements or during product transportation, chips may occur, especially at the corners and edges of the outer peripheral edge of the package. Cracks often occur, reducing reliability.
As a result, this resulted in a loss of marketability. Conventional ceramic substrates for semiconductor packages can be prevented from chipping and cracking to a certain extent compared to those formed simply in the form of a rectangular parallelepiped and flat plate. I can't hold back,
In this sense, there was a drawback that the yield of the product was low. The present invention was devised in view of the above-mentioned problems of the prior art, and its purpose is to prevent the edges and corners of ceramic substrates from being chipped during the assembly process of semiconductor devices and during product transportation. It is an object of the present invention to provide a ceramic substrate which has a very good yield of products because the occurrence of chips and cracks is extremely rare, and even when chips and cracks occur, the size of chips and cracks is extremely small. [Means for Solving the Problems] In order to achieve the above object, the ceramic substrate of the present invention has a cavity portion for accommodating a semiconductor element, and has a semiconductor substrate having a slightly rounded corner on its outer peripheral end surface. A ceramic substrate for a package, the ceramic substrate having a minute step along the outer periphery of the ceramic substrate at an edge on an end surface opposite to the surface in which the cavity portion is bored.
forming two step portions and three rounded ridge portions;
L 1 and the width L 2 of the second portion on the lower side are formed in a relationship such that L 1 ≫L 2 . [Example] An example will be described with reference to the drawings. 1 to 3, a ceramic substrate 1 for a semiconductor package has a width of 2 cm, a length of 5 cm, and a thickness of
It is formed in the shape of a rectangular parallelepiped plate with a diameter of 1.5 mm.
One end (side surface) in the longitudinal direction has a radius of approximately 1 mm.
A semicircular automatic insertion notch 2 is formed. The corners 3 of the outer peripheral end surface of this ceramic substrate 1 are each rounded with a radius of about 0.4 mm, and the corners 3 are rounded with a radius of approximately 0.4 mm, and the corners 3 are rounded on the opposite side to the surface where the cavity portion 4 for accommodating the semiconductor element A is formed. The edge 5 at the end surface of the surface has two step portions 6 and 7 along the outer periphery of the ceramic substrate 1, each having a minute step of about 0.1 mm, and a radius.
Three ridges 8 with roundness of about 0.04 to 0.06 mm,
9 and 10 are formed, and the width L 1 of the first step 6 on the upper side and the width L 2 of the second step 7 on the lower side are L 1
≫It is formed in the relationship of L 2 (see Figure 3). The code 1A indicates a cap made of a ceramic substrate.
1B indicates a base having the same shape as the cap 1A. 1
1 is a sealing glass that adheres the cap 1A and the base 1B and hermetically seals the inside of the package.
Further, 12 is a lead frame. The ceramic substrate 1 configured as described above is
Even if the ceramic substrates 1 randomly collide with each other during the assembly process of semiconductor packages or the process of transporting assembled semiconductor packages, the impact force applied to the corners 3 will be small because the corners 3 are rounded. The corners 3 are softened and therefore less prone to chipping and cracking, and the edges 5 are rounded ridges 8,
9 and 10 with two step parts 6 and 7, the impact force applied to the edge 5 is dispersed and alleviated by the three ridge parts 8, 9, and 10. Edge 5 is also less prone to chips and cracks. When impact tests were conducted on semiconductor packages assembled using the ceramic substrates described in the above embodiments, test results as shown in Table 1 were obtained.
【表】
試験方法は、第4図に示す従来のセラミツク基
板を用いて組み立てた半導体パツケージと、本考
案の実施例に係るセラミツク基板1を用いて組み
立てた半導体パツケージをそれぞれ100セツト組
み立て、従来のセラミツク基板を用いて組み立て
た半導体パツケージと、本考案の実施例に係るセ
ラミツク基板1を用いて組み立てた半導体パツケ
ージについて、1個ずつ長さ50cm、断面凹形の中
空筒体として形成されたプラスチツク製の半導体
パツケージ保管チユーブに収納し、該チユーブの
両端面に同質材のセラミツク基板を被蓋した後、
該チユーブを上下の方向に、1秒間に180度の角
速度をもつて、10回繰り返し回転させて、欠けや
亀裂を生じた半導体パツケージの個数を調べたも
のである。
このテーブル1から明らかなように、従来のセ
ラミツク基板を用いて組み立てた半導体パツケー
ジは平均6.3回の衝突で合計100組中3個について
欠け、亀裂が発生しているのに対して、本考案の
実施例に係るセラミツク基板1を用いて組み立て
た半導体パツケージにおいては平均8.5回の衝突
で100個中2個の欠け、亀裂しか発生しておらず、
しかも、ほとんどが半導体パツケージ基板の長手
方向と直交する外周端面のエツジに極めて微少な
サイズで発生しているだけであつた。
更にセラミツク基板の外周に沿つて微少な段差
を有する2つの段部と丸味を施した3つの稜部を
もつて形成されいるセラミツク基板A,B,C,
D(2つの段部の上方側の幅L1と下方側の第2の
段部の幅L2との関係を変えた試料)を用いて組
み立てた半導体パツケジをそれぞれ100セツト組
み立て、前述の試験方法により同様の衝撃試験を
行つたところ、テーブル2のような試験結果が得
られた。[Table] The test method was to assemble 100 sets of semiconductor packages assembled using the conventional ceramic substrate shown in Fig. 4 and 100 sets of semiconductor packages assembled using the ceramic substrate 1 according to the embodiment of the present invention. Regarding the semiconductor package assembled using a ceramic substrate and the semiconductor package assembled using the ceramic substrate 1 according to the embodiment of the present invention, each semiconductor package was made of plastic formed as a hollow cylinder with a length of 50 cm and a concave cross section. After storing the semiconductor package in a semiconductor package storage tube and covering both end surfaces of the tube with ceramic substrates made of the same material,
The tube was repeatedly rotated 10 times in the vertical direction at an angular velocity of 180 degrees per second, and the number of chipped or cracked semiconductor packages was determined. As is clear from Table 1, semiconductor packages assembled using conventional ceramic substrates were hit an average of 6.3 times, resulting in chipping and cracking in 3 out of 100 packages, whereas the present invention's In the semiconductor packages assembled using the ceramic substrate 1 according to the example, only 2 out of 100 chips or cracks occurred after an average of 8.5 collisions.
Moreover, most of the particles were generated in extremely small sizes at the edges of the outer peripheral end face perpendicular to the longitudinal direction of the semiconductor package substrate. Further, ceramic substrates A, B, C, which are formed with two step portions having minute steps and three rounded ridge portions along the outer periphery of the ceramic substrate.
100 sets of each semiconductor package were assembled using D (a sample in which the relationship between the upper width L 1 of the two steps and the width L 2 of the lower second step) was assembled, and the above-mentioned test was performed. When a similar impact test was conducted using the same method, the test results shown in Table 2 were obtained.
【表】【table】
本考案は、上述のとおり構成されているので、
次に記載する効果を奏する。
セラミツク基板の外周端部に幅の異なる2つの
段部を形成することにより、エツジに加わる衝撃
力を分散し弱めることができるため、セラミツク
基板が衝突すること等によつて発生する欠け、亀
裂の発生を減少させることができるとともに、欠
け等の大きさを極く微少なものにとどめることが
可能である。
又、段部を2段形成したために、成型時にセラ
ミツク基板の端部への成形圧力を強くとることが
出来、パツケージのエツジの強度を高めることが
可能である。
Since the present invention is configured as described above,
This produces the following effects. By forming two steps with different widths on the outer peripheral edge of the ceramic substrate, it is possible to disperse and weaken the impact force applied to the edge, thereby preventing chips and cracks that occur due to collisions between the ceramic substrates. It is possible to reduce the occurrence of chips, and to keep the size of chips etc. to be extremely small. Further, since the stepped portion is formed in two stages, it is possible to apply strong molding pressure to the end portion of the ceramic substrate during molding, and it is possible to increase the strength of the edge of the package.
第1図は本考案に係るセラミツク基板を用いて
形成した半導体パツケージの斜視図、第2図はそ
の横断面拡大図、第3図は本考案に係るセラミツ
ク基板の要部拡大断面略図、第4図は従来のセラ
ミツク基板の要部拡大断面略図である。
FIG. 1 is a perspective view of a semiconductor package formed using a ceramic substrate according to the present invention, FIG. 2 is an enlarged cross-sectional view thereof, FIG. The figure is a schematic enlarged cross-sectional view of the main part of a conventional ceramic substrate.
Claims (1)
の外周端面のコーナーに微少な丸味が施されてい
る半導体パツケージ用のセラミツク基板であつ
て、前記キヤビテイ部が穿設された面と反対側の
端面におけるエツジに、前記セラミツク基板の外
周に沿つて、微少な段差を有する2つの段部と丸
味を施した3つの稜部を形成し、しかも前記2つ
の段部を、上方側の第1の段部の幅L1と、下方
側の第2段部の幅L2とをL1≫L2の関係に形成し
たことを特徴とするセラミツク基板。 A ceramic substrate for a semiconductor package, which has a cavity portion for accommodating a semiconductor element, and has a slightly rounded corner on its outer peripheral end surface, the end surface being opposite to the surface where the cavity portion is bored. Two step portions having a slight step and three rounded ridge portions are formed on the edge along the outer periphery of the ceramic substrate, and the two step portions are connected to the first step portion on the upper side. 1. A ceramic substrate characterized in that a width L 1 of the lower second step portion and a width L 2 of the second step portion on the lower side are formed in a relationship such that L 1 ≫L 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988063301U JPH0451485Y2 (en) | 1988-05-16 | 1988-05-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988063301U JPH0451485Y2 (en) | 1988-05-16 | 1988-05-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01167052U JPH01167052U (en) | 1989-11-22 |
| JPH0451485Y2 true JPH0451485Y2 (en) | 1992-12-03 |
Family
ID=31288809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988063301U Expired JPH0451485Y2 (en) | 1988-05-16 | 1988-05-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451485Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0731549Y2 (en) * | 1988-11-11 | 1995-07-19 | 京セラ株式会社 | Ceramic substrate for semiconductor package |
| JP5617574B2 (en) * | 2010-12-01 | 2014-11-05 | 株式会社村田製作所 | Ceramic multilayer substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5572064A (en) * | 1978-11-25 | 1980-05-30 | Kyocera Corp | Ceramic substrate |
| JPS5750062A (en) * | 1980-09-09 | 1982-03-24 | Toshiba Corp | Magnetic disk controller |
-
1988
- 1988-05-16 JP JP1988063301U patent/JPH0451485Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01167052U (en) | 1989-11-22 |
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