JPH0451513A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0451513A JPH0451513A JP2161006A JP16100690A JPH0451513A JP H0451513 A JPH0451513 A JP H0451513A JP 2161006 A JP2161006 A JP 2161006A JP 16100690 A JP16100690 A JP 16100690A JP H0451513 A JPH0451513 A JP H0451513A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- photomask
- measuring
- dimensions
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000005259 measurement Methods 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置の製造用フォトマスクに
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photomask for manufacturing semiconductor integrated circuit devices.
本発明は、半導体集積回路装置の製造用フォトマスクに
おいて、指定寸法を測定するためのパターンを各機能セ
ル毎に設けることによって、機能セルが描画合成された
フォトマスクの寸法の誤差を許容範囲内に納めるように
したものである。In a photomask for manufacturing semiconductor integrated circuit devices, the present invention provides a pattern for measuring a specified dimension for each functional cell, thereby reducing errors in dimensions of a photomask on which functional cells are drawn and synthesized within an allowable range. It was designed to fit in.
第２図は従来技術による半導体集積回路装置の製造用フ
ォトマスクの概略図である。機能セルが１つの時の、２
１はフォトマスクを構成している機能セル、２５は機能
セル２１に配置された指定寸法測定用のパターンである
。指定寸法を測定するためのパターンは、データ描画後
のフォトマスクの仕上がり寸法もしくは半導体製造時の
ウェハーの仕上がり寸法の測定用として、機能セルの任
意の場所に配置していた。フォトマスクでの指定寸法は
、描画前の測定用パターンの寸法と描画後の測定用パタ
ーンの寸法とを比較して、誤差が許容範囲内であるかを
検査するのに用いていた。FIG. 2 is a schematic diagram of a photomask for manufacturing a semiconductor integrated circuit device according to the prior art. 2 when there is one functional cell
1 is a functional cell constituting a photomask, and 25 is a pattern for measuring specified dimensions arranged in the functional cell 21. A pattern for measuring a designated dimension is placed at an arbitrary location in a functional cell for measuring the finished dimension of a photomask after data writing or the finished dimension of a wafer during semiconductor manufacturing. The specified dimensions on the photomask were used to compare the dimensions of the measurement pattern before writing and the dimensions of the measurement pattern after writing to check whether the error was within an allowable range.
しかし、近年半導体業界では、より付加価値の高い製品
を提供するために、半導体記憶回路（ＲＡＭ、ＲＯＭ、
またはそれに似た機能を持つ回路） ヲ内蔵したマイク
ロプロセッサ−などの大規模な回路の開発が著しい。こ
れらマイクロプロセッサ−には、集積度の大きい記憶回
路やあらゆる演算処理を行う制御回路が多数台まれ、マ
イクロプロセッサ−を構成する回路素子数は莫大なもの
となる。そして、描画装置の制約からこのような大規模
な回路は、１つの機能セルとしてフォトマスクに描画す
る前に合成することができない。However, in recent years, in the semiconductor industry, in order to provide products with higher added value, semiconductor memory circuits (RAM, ROM,
(or circuits with similar functions) The development of large-scale circuits such as built-in microprocessors is remarkable. These microprocessors are equipped with a large number of highly integrated memory circuits and control circuits that perform all kinds of arithmetic processing, and the number of circuit elements making up the microprocessor is enormous. Due to limitations of the drawing device, such a large-scale circuit cannot be synthesized before being drawn on a photomask as one functional cell.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは回路規模に応じて複数の機能セル
に分割し、かつマスクを構成する全ての機能セルに対し
てご仕上がり寸法の誤差を少なくした半導体集積回路装
置を提供するところにある。The present invention is intended to solve these problems.The purpose of the present invention is to divide the circuit into multiple functional cells according to the scale of the circuit, and to adjust the finished dimensions of all the functional cells constituting the mask. An object of the present invention is to provide a semiconductor integrated circuit device with reduced errors.
（ｉｆｌを解決するための手段〕
本発明の半導体集積回路装置は、フォトマスクに描画合
成される複数の機能セルを有し、各機能セル毎に指定寸
法を測定するためのパターンを設けたことを特徴とする
。(Means for solving ifl) The semiconductor integrated circuit device of the present invention has a plurality of functional cells drawn and synthesized on a photomask, and a pattern for measuring a specified dimension is provided for each functional cell. It is characterized by
第１図は本発明の実施例における複数の機能セルを有し
、かつ全ての機能セルに指定寸法を測定するためのパタ
ーンを設けた、描画合成時のフォトマスクの概略図であ
る。FIG. 1 is a schematic diagram of a photomask at the time of drawing synthesis, which has a plurality of functional cells and in which all functional cells are provided with a pattern for measuring specified dimensions, according to an embodiment of the present invention.
本発明においては、大規模な回路を複数のブロックに分
割し、各々のブロックを１つ１つの機能セルとして割り
当て、回路を構成している全ての機能セル毎に指定寸法
を測定するためのパターンを設ける。これら複数の機能
セルをある１つのマスクについて描画合成して得られた
フォトマスクの概略図が第１図であり、１，２，５．４
はフォトマスクを構成している各々が１つの機能セル、
５．６は機能セル１に配置された指定寸法測定用のパタ
ーン、７は機能セル２に配置された指定寸法測定用のパ
ターン、８，９は機能セル６に配置された指定寸法測定
用のパターン、１０は機能セル４に配置された指定寸法
測定用のパターンである。In the present invention, a large-scale circuit is divided into a plurality of blocks, each block is assigned as a single functional cell, and a pattern is created to measure specified dimensions for each functional cell that constitutes the circuit. will be established. Figure 1 is a schematic diagram of a photomask obtained by drawing and synthesizing these multiple functional cells for one mask.
are each one functional cell constituting the photomask,
5 and 6 are patterns for measuring specified dimensions placed in functional cell 1, 7 are patterns for measuring specified dimensions placed in functional cell 2, and 8 and 9 are patterns for measuring specified dimensions placed in functional cell 6. A pattern 10 is a pattern arranged in the functional cell 4 for measuring specified dimensions.
ここで示しである機能セルは、回路全体の規模によって
分割されるので、いくつもの機能セルが存在してもかま
わない。また各々の機能セルに含まれている指定寸法を
測定するパターンとしては、本実施例ではＹ字形のパタ
ーンを用いたが、寸法を測定するのに便利な形状であれ
ばいかなるパターンでもよく、配置する数は最低１つ以
上であればよい。配置する位置及び向きは、そのマスク
を構成しているデザインルールを満足する範囲内であれ
ばよい。The functional cells shown here are divided according to the scale of the entire circuit, so it does not matter how many functional cells there may be. In addition, although a Y-shaped pattern was used in this embodiment as a pattern for measuring the specified dimensions included in each functional cell, any pattern may be used as long as it is convenient for measuring dimensions. The number may be at least one. The position and orientation of the mask may be within a range that satisfies the design rules constituting the mask.
尚、寸法測定用のパターンは、半導体製造に必要なフォ
トマスク全てに設ける必要はなく、描画合成による仕上
がり寸法が高精度を要求されるフォトマスクに設けるだ
けでもかまわない。Note that the pattern for dimension measurement does not need to be provided on all photomasks necessary for semiconductor manufacturing, and may be provided only on photomasks that require high precision in finished dimensions by drawing synthesis.
以上述べたように本発明によれば、回路全体の規模によ
って分割した機能セル毎に指定寸法を測定するためのパ
ターンを設けることＫよって、全ての機能セルの仕上が
り寸法を許容範囲内にすることができるので、フォトマ
スク製造時の加工不良が半導体製造時の不良原因に含ま
れなくなり、歩留まりの向上が計れるという効果を有す
る。As described above, according to the present invention, by providing a pattern for measuring specified dimensions for each functional cell divided according to the scale of the entire circuit, the finished dimensions of all functional cells can be kept within an allowable range. This has the effect that processing defects during photomask manufacturing are no longer included in the causes of defects during semiconductor manufacturing, and yield can be improved.
更に寸法を測定するためのパターンの個数及び位置は任
意に決められるので、高い精度が要求される回路付近に
置（ことにより、その機能セル内での仕上がり寸法のば
らつきを抑えることができるという効果を有する。Furthermore, since the number and position of patterns for measuring dimensions can be arbitrarily determined, it is possible to place them near circuits that require high precision (this has the effect of suppressing variations in finished dimensions within the functional cell). has.
また半導体製造時においても、この指定寸法を用いるこ
とで、各製造プロセスの加工精度を測定できるという効
果も有する。Further, even during semiconductor manufacturing, by using the specified dimensions, it is possible to measure the processing accuracy of each manufacturing process.
第１図は本発明の実施例を示すフォトマスク概略図。第
２因は従来の例を示すフォトマスク概略図。
１〜４−−・−指定寸法測定用のパターンが配置された
機能セル
５〜１０−一指定寸法測定用のパターン−・・・−機能
セル
−・−・・−前走寸法測定用のパターン以
上FIG. 1 is a schematic diagram of a photomask showing an embodiment of the present invention. The second factor is a schematic diagram of a photomask showing a conventional example. 1 to 4 - Functional cells in which patterns for measuring specified dimensions are arranged 5 to 10 - Patterns for measuring specified dimensions - Functional cells - Patterns for measuring forward dimensions that's all
Claims (1)
各機能セル毎に指定寸法を測定するためのパターンを設
けたことを特徴とする半導体集積回路装置。It has multiple functional cells that are drawn and synthesized on a photomask,
A semiconductor integrated circuit device characterized in that a pattern is provided for measuring specified dimensions for each functional cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161006A JPH0451513A (en) | 1990-06-19 | 1990-06-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161006A JPH0451513A (en) | 1990-06-19 | 1990-06-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451513A true JPH0451513A (en) | 1992-02-20 |
Family
ID=15726790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2161006A Pending JPH0451513A (en) | 1990-06-19 | 1990-06-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451513A (en) |
-
1990
- 1990-06-19 JP JP2161006A patent/JPH0451513A/en active Pending
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