JPH0451511A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0451511A
JPH0451511A JP2161004A JP16100490A JPH0451511A JP H0451511 A JPH0451511 A JP H0451511A JP 2161004 A JP2161004 A JP 2161004A JP 16100490 A JP16100490 A JP 16100490A JP H0451511 A JPH0451511 A JP H0451511A
Authority
JP
Japan
Prior art keywords
photomask
pattern
functional
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2161004A
Other languages
Japanese (ja)
Inventor
Shoichiro Kasahara
昌一郎 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2161004A priority Critical patent/JPH0451511A/en
Publication of JPH0451511A publication Critical patent/JPH0451511A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • H10W46/101Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device, which decreases the slippages during the composition of drawings by providing each function cell with patterns for detecting the dislocation at the time of compositing the drawings of a plurality of function cells. CONSTITUTION:Each photomask is constituted of a function cell 1, 2, 3, or 4. And in the function cell 1 are arranged patterns 5, 6, 7 and 8 for slippage ditection, and in the function cell 2 are arranged patterns 10 and 11 for slippage detection, and in the function cell 3 is arranged a pattern 12 for detection, and in the function cell 4 is arranged the one 13 for slippage detection.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置の製造用フォトマスクに
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photomask for manufacturing semiconductor integrated circuit devices.

〔発明の概要〕[Summary of the invention]

本発明は、半導体集積回路装置の製造用フォトマスクに
おいて、機能セルを描画合成する際のずれを検出するパ
ターンを各機能セル毎に設けることによって、描画合成
する際のずれを検出する方法を備えフォトマスクでの機
能セルの描画合成する際のずれを許容範囲内に納めたも
のである。
The present invention includes a method for detecting deviations during drawing and synthesis of functional cells by providing a pattern for each functional cell to detect deviations during drawing and synthesis of functional cells in a photomask for manufacturing semiconductor integrated circuit devices. This is to keep the deviation during drawing and synthesis of functional cells using a photomask within an allowable range.

〔従来の技術〕[Conventional technology]

第2図は従来の半導体集積回路装置の製造用フォトマス
クにおける概略図である。従来、機能セルを描画合成す
る際のずれを検出するパターンはフォトマスクにおける
ゲータ描画時の描画合成精度の検出用パターンもしくは
、機能セルのデータ領域の目視確認用パターンとして、
機能セルのデータ領域の4隅などに配置していた。描画
合成精度の判定としては、フォトマスクに描画前のデー
タにおける検出用パターンと、描画後のフォトマスクに
おける検出用パターンとの位置を測定し、ずれを許容範
囲内に納めていた。
FIG. 2 is a schematic diagram of a conventional photomask for manufacturing semiconductor integrated circuit devices. Conventionally, the pattern for detecting deviations when drawing and synthesizing functional cells has been used as a pattern for detecting drawing synthesis accuracy during gator drawing on a photomask, or as a pattern for visual confirmation of the data area of functional cells.
They were placed at the four corners of the data area of the functional cell. To determine the drawing synthesis accuracy, the positions of the detection pattern in the data before drawing on the photomask and the detection pattern in the photomask after drawing were measured, and the deviation was kept within an allowable range.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第2図はフォトマスクに描画する機能セルが1つのデー
タの時の、フォトマスクの概略図である。
FIG. 2 is a schematic diagram of a photomask when the number of functional cells drawn on the photomask is one piece of data.

第2図において、21はフォトマスクを構成している機
能セル、25,26,27.28は機能セル21に配置
されたずれ検出用の、<ターンである。ずれ検出用パタ
ーン25.26.27.28は、機能セル21のデータ
領域を目視確認するためにも使用できる。この場合機能
セルを描画合成する際のずれは、許容範囲内で生じる以
外は、大きなずれが生じるという問題は少なかった。
In FIG. 2, 21 is a functional cell constituting a photomask, and 25, 26, 27, and 28 are < turns arranged in the functional cell 21 for detecting deviation. The deviation detection patterns 25, 26, 27, and 28 can also be used to visually confirm the data area of the functional cell 21. In this case, the problem of large deviations occurring when drawing and synthesizing the functional cells was small, except that the deviations occurred within the allowable range.

最近半導体業界では、より付加価値の高い製品を提供す
るために、半導体記憶回路(RAM、ROM、またはそ
れに似た機能を持つ回路)を内蔵したマイクロプロセッ
サ−などの大規模な回路の開発が著しい。これらマイク
ロプロセッサ−には、集積度の大きい記憶回路や、あら
ゆる演算処理を行う制御回路が多数含まれ、マイクロプ
ロセンサーを構成する回路素子数は、莫大なものとなる
しかし、描画装置の制約からこのような大規模な回路は
、1つの機能セルとしてフォトマスクに描画する前に合
成することができないため1.第1図の方法を用いるこ
とはできなかった。
Recently, in the semiconductor industry, there has been a remarkable development of large-scale circuits such as microprocessors with built-in semiconductor memory circuits (RAM, ROM, or circuits with similar functions) in order to provide products with higher added value. . These microprocessors include a large number of highly integrated memory circuits and control circuits that perform all kinds of arithmetic processing, and the number of circuit elements that make up the microprocessor is enormous. However, due to the limitations of the drawing device, 1. Such a large-scale circuit cannot be synthesized as a single functional cell before being drawn on a photomask. It was not possible to use the method shown in FIG.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところはマスクを構成する全ての機能セル
に対して、描画合成する際に生じるずれを少なくした半
導体集積回路装置を提供するところにある。
The present invention is intended to solve these problems, and its purpose is to provide a semiconductor integrated circuit device that reduces deviations that occur during drawing and synthesis for all functional cells constituting a mask. It's there.

L課題を解決するための手段〕 本発明の半導体集積回路装置は、フォトマスクに描画合
成される複数の機能セルを有し、各機能セル毎に複数の
機能セルを描画合成する際のずれを検出するためのパタ
ーンを設げたことを特徴とする。
Means for Solving Problem L] The semiconductor integrated circuit device of the present invention has a plurality of functional cells that are drawn and synthesized on a photomask, and the deviation in drawing and synthesis of the plurality of functional cells is corrected for each functional cell. It is characterized by providing a pattern for detection.

〔実施例〕〔Example〕

第1図は本発明の実施例における複数の機能セルを有し
、かつ全ての機能セルに描画合成する際のずれを検出す
るためのパターンを設けた、描画合成時のフォトマスク
の概略図である。
FIG. 1 is a schematic diagram of a photomask during drawing synthesis in an embodiment of the present invention, which has a plurality of functional cells and is provided with a pattern for detecting deviation during drawing synthesis on all the functional cells. be.

従来の問題点を解決するため本発明のように、大規模な
回路を複数のブロックに分割し、各々のブロックを1つ
1つの機能セルとして割り当て、回路を構成している全
ての機能セル毎にずれを検出するパターンを設ける。こ
の場合、フォトマスクに描画するまでは回路全体として
のデータの合成は成されない。これら複数の機能セルを
ある1つのマスクについて描画合成して得られたフォト
マスクの概略図は、第1図のようになる。第1図におい
て、1p2t5*4はフォトマスクを構成している各々
が1つの機能セル、 5 t 6 * 7 m B’、
9は機能セル1に配置されたずれ検出用のパターン、1
0.11は機能セル2に配置されたずれ検出用のパター
ン、12は機能セル6に配置されたずれ検出用のパター
ン、16は1つの機能セル4に配置されたずれ検出用の
パターンである。ここで示しである機能セルは、回路全
体の規模によってい(つかに分割するので、いくつもの
機能セルが存在してもかまわない。また各々の機能セル
に含まれているずれを検出するパターンは、本実施例で
はL字形のパターンを用いているが、ずれを検出するの
に便利な形状であれば、いかなる)ぐターンでもかまわ
ない。また各々の機能セルに配置するずれ検出用のパタ
ーンの数は、最低1つ、必要に応じては1つ以上いれる
ことが可能であるまた各々の機能セルに配置するずれ検
出用のパターンの位置及びそのパターンの方向は、その
マスクを構成しているデザインルールを満足する範囲内
であればよい。なお、ずれ検出用のパターンは、半導体
製造に必要なフォトマスク全てに配置する必要はなく、
描画合成に高精度を要求されるフォトマスクに配置する
だけでもかまわない。
In order to solve the conventional problems, as in the present invention, a large-scale circuit is divided into multiple blocks, each block is assigned as a single functional cell, and each functional cell constituting the circuit is A pattern is provided to detect deviation. In this case, the data for the entire circuit is not synthesized until it is drawn on the photomask. A schematic diagram of a photomask obtained by drawing and combining these plurality of functional cells for one mask is shown in FIG. In FIG. 1, 1p2t5*4 each constitutes a photomask and has one functional cell, 5t6*7m B',
9 is a pattern for detecting deviation arranged in functional cell 1, 1
0.11 is a pattern for detecting deviation placed in functional cell 2, 12 is a pattern for detecting deviation placed in functional cell 6, and 16 is a pattern for detecting deviation placed in one functional cell 4. . The functional cells shown here are divided into parts according to the scale of the entire circuit, so it does not matter how many functional cells there may be. Although an L-shaped pattern is used in this embodiment, any shape may be used as long as it is convenient for detecting deviation. In addition, the number of patterns for detecting deviations placed in each functional cell is at least one, and it is possible to place more than one if necessary.Also, the number of patterns for detecting deviations placed in each functional cell is The direction of the pattern may be within a range that satisfies the design rules constituting the mask. Note that the pattern for detecting misalignment does not need to be placed on all photomasks required for semiconductor manufacturing;
It is also possible to simply place it on a photomask that requires high accuracy in drawing synthesis.

〔発明の効果〕〔Effect of the invention〕

以上述べたように発明によれば、回路全体の規模によっ
て分割した機能セル毎に、複数の機能セルを描画合成す
る際のずれを検出するための〆桑−ンを設けることによ
り、全ての機能セルのずれを許容範囲内に納められ、フ
ォトマスクの描画合成時におけるデータ挿入の精度を高
めることができるという効果を有する。そして、ずれを
検出するパターンの個数及び位置は、任意に決められろ
ので、より精度が重要となる回路付近に置(ことにより
、フォトマスク製造時の加工不良が、半導体製造時の不
良原因に含まれなくなり、歩留まりの向上が計れるとい
う効果を有する。また、・各機能セル毎に配置されたず
れを検出するパターンを用いることにより、その機能セ
ル毎のデータの有無を目視により確認することができる
という効果も有する。
As described above, according to the invention, by providing a check mark for detecting deviations when drawing and synthesizing multiple functional cells for each functional cell divided according to the scale of the entire circuit, all functions can be This has the effect that the cell misalignment can be kept within an allowable range, and the accuracy of data insertion during photomask drawing synthesis can be improved. The number and position of patterns for detecting misalignment can be determined arbitrarily, so they should be placed near circuits where accuracy is more important (thereby, machining defects during photomask manufacturing may be the cause of defects during semiconductor manufacturing). This has the effect of improving the yield.In addition, by using a pattern that detects the misalignment of each functional cell, it is possible to visually confirm whether or not there is data for each functional cell. It also has the effect of being able to do so.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すフォトマスク概略図。第
2図は従来の例を示すフォトマスク概略図。 1〜4−・−一・ずれ検出用のパターンが配置された機
能セル 5〜13−・−ずれ検出用のパターン 21−−−一機能セル 25〜28−ずれ検出用のパターン 第
FIG. 1 is a schematic diagram of a photomask showing an embodiment of the present invention. FIG. 2 is a schematic diagram of a photomask showing a conventional example. 1 to 4--1.Functional cells 5 to 13 in which patterns for deviation detection are arranged--Patterns for deviation detection 21--Functional cells 25 to 28-Patterns for deviation detection No.

Claims (1)

【特許請求の範囲】[Claims] フォトマスクに描画合成される複数の機能セルを有し、
各機能セル毎に複数の機能セルを描画合成する際のずれ
を検出するためのパターンを設けたことを特徴とする半
導体集積回路装置。
It has multiple functional cells that are drawn and synthesized on a photomask,
1. A semiconductor integrated circuit device, characterized in that each functional cell is provided with a pattern for detecting deviations when drawing and synthesizing a plurality of functional cells.
JP2161004A 1990-06-19 1990-06-19 Semiconductor integrated circuit device Pending JPH0451511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2161004A JPH0451511A (en) 1990-06-19 1990-06-19 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2161004A JPH0451511A (en) 1990-06-19 1990-06-19 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0451511A true JPH0451511A (en) 1992-02-20

Family

ID=15726750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2161004A Pending JPH0451511A (en) 1990-06-19 1990-06-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0451511A (en)

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