JPH0451786A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To easily suppress fixed pattern noise without provision of a reset transistor(TR) and a 1H memory for each picture element by subtracting a optical storage signal output of a same picture element and a picture element signal just after resetting so as to suppress the fixed pattern noise. CONSTITUTION:A delay element 2a of a fixed pattern noise suppression circuit section 2 delays a phase of an output signal V1 to make the phase coincident with the relevant phase of an output signal V2 just after reset of a same picture element, a differential amplifier circuit 2b subtracts the signals to eliminate ununiform output offset components N11, N12,... caused by not uniform characteristic of each picture element and to obtain a correction output signal OUT with excellent S/N only from output signal components S11, S12,.... Thus, a reset transistor(TR) and a 1H memory for each picture element are not required to reduce the area of the scanning circuit or the chip area to reduce the cost thereby easily suppressing fixed pattern noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device that suppresses fixed pattern noise and uses an imaging element having an amplification function as a pixel.

[Conventional technology]

Generally, in a solid-state imaging device that uses an imaging element with an amplification function as a pixel, the offset and gain of the amplification section of each pixel are different, so the output of the imaging device contains a lot of fixed pattern noise. For example, in the case of an FET type amplification section, the main cause is variation in the amplification operation start voltage, which corresponds to the variation in output when the photodiode on the gate side is not irradiated with light. Therefore, fixed pattern noise occurs when there is little light input, and fixed pattern noise is detected when capturing images with low illuminance, degrading the image quality.

On the other hand, fixed pattern noise caused by a difference in the gain of the amplification section is a fixed pattern noise that occurs in proportion to the input of light, and is small in dark scenes and has a low detection limit. (Reference: “Study on the detection limit characteristics of fixed pattern noise in solid-state image sensors”, Proceedings of the National Conference of the Society of Television Engineers, 2-10.1989) Therefore, conventionally, regarding the method of removing fixed pattern noise due to the offset component, the following Many proposals have been made as shown below.

(1) A method has been proposed in which the output when no light is input is stored in a two-dimensional memory and the memory output is subtracted from the optical accumulation output signal of the image sensor to suppress fixed pattern noise.

(2) Also, as one of the conventional proposed technologies, an amplification type image sensor B A S I S (Base 5 tore Im
age 5 sensor). This technology is
In a Y-address type two-dimensional image sensor, an analog line memory for one horizontal line (IH) is provided in the element,
Immediately after recording the optical accumulation output signal from the pixel for 18 minutes,
Fixed pattern noise is reduced by reading out the black signal based on the recency of the optical signal charge and at the same time calculating the difference from the signal previously recorded in the line memory. (Reference: “A Novel Bipolar I
□evice @ith 5el
fNoise Reduction Capabili
ty” IEEE ED ν01゜36, No.
1. N0BUYO5HI TANAKA January
ry 1989) (3) Furthermore, as one of the conventional technologies, FGA (Floating Gate Arre
There is something related to y). This technology separates vertical signal lines with capacitors in an X-Y address type two-dimensional image sensor, clamps the reset signal output for each IH (7), that is, the black part, and then samples the signal components. It is something.

This is equivalent to subtracting the black signal from the optical accumulation output signal, and fixed pattern noise is suppressed. (Reference: 'A NEW DEVICEEAR(
JIITECTURE 5UITABLE FOR) I
IGH-RESOLUTIONAND )IIGH-
PERFORMANCE” JARO5LAV H
YNECEKIEEE ED Vol, I35. No
, 5. May 1988. PI), 646-6
52) (4) Another example of the prior art is the point-sequential time-division differential system. In this method, a reset transistor is provided for each pixel in an X-Y address type two-dimensional image sensor, and the reset is performed in the middle of the readout period of one pixel, and the light accumulation signal output and black output are continuously output. reading,
This method suppresses fixed pattern noise by subtraction. (Reference: Japanese Patent Application No. 62-273052
[Problems to be Solved by the Invention] As mentioned above, many proposals have been made regarding methods of suppressing fixed pattern noise using offset components, but each of the proposed techniques has the following drawbacks. have.

First, although the method of suppressing fixed pattern noise using an external memory (Section 11) has high cancellation accuracy, it increases the scale of the circuit and is disadvantageous in terms of power consumption and cost.

(2) Suppressing fixed pattern noise inside the element B
In the example of ASIS, although the disadvantages of the technique shown in item (1) above can be overcome, it is difficult to remove vertical streak-like fixed pattern noise generated from IH memory. This is because there are variations in the capacitance provided for storing the output of each pixel in the IH memory, and as a result, fixed pattern noise in the form of vertical stripes is unavoidable. A similar drawback also exists in the method using FGA described in (3). The problem of such fixed pattern noise in the form of vertical stripes arises from imperfections in the noise cancellation method itself.

As mentioned above, most fixed pattern noise suppression methods using offset components involve resetting the element or turning off the optical input to form a state with no photocharge, and then subtracting the eight sides in that state from the signal component. It is based on the principle of In the current technology, since the method of resetting an element requires a 1H period due to its structure, utilizing the above principle necessarily requires a memory for an IH period. Therefore, since the memory is an IH memory, variations from pixel to pixel in each memory are likely to be detected as fixed pattern noise in the form of vertical stripes.

Further, the point-sequential time-division differential method, which does not require an IH memory, as described in item (4) above, has the disadvantage that a reset transistor is not provided for each pixel, and the device configuration becomes very complicated. Furthermore, when driving the element at a high frequency, the readout period for one pixel becomes short, and it is difficult to perform a series of operations such as signal readout during one pixel period, reset, and signal readout immediately after reset.

The present invention was made in order to solve the above-mentioned problems in conventional solid-state imaging devices that suppress fixed pattern noise, and it is possible to easily suppress fixed pattern noise without providing a cent transistor or IH memory for each pixel. An object of the present invention is to provide a solid-state imaging device.

(Means and effects for solving the problem) In order to solve the above problems, the present invention provides a solid-state imaging device in which image sensors having an amplification function are arranged as pixels in a two-dimensional or one-dimensional manner, in which each pixel a first horizontal selection circuit that sequentially reads out the optical accumulation signals of each pixel; and a reset operation after reading out the optical accumulation signals by the first horizontal selection circuit of each pixel, and an operation of reading out the pixel signals immediately after the reset operation. and a means for reducing fixed pattern noise contained in the light accumulation signal of each pixel by subtracting the light accumulation signal of the same pixel from the pixel signal immediately after the centration operation. It is.

In the solid-state imaging device configured in this way, the light accumulation signal output of each pixel is read out by the operation of the first horizontal selection circuit, and then the optical accumulation signal output of each pixel for which the readout operation has been completed is read out by the operation of the second horizontal selection circuit. is reset, and the pixel signal immediately after the reset is read out. Then, the power of the light accumulation signal output of the same pixel and the pixel signal immediately after reset is reduced, and a signal output with fixed pattern noise suppressed is output.

This creates a special reset transistor for each pixel and an I
A solid-state imaging device that does not require an H memory and can easily suppress fixed pattern noise can be realized. In addition, in the present invention, the readout of the optical accumulation signal output 5, the reset, and the readout of the pixel signal immediately after the reset can be performed at different timings, so it is effective even when the readout period of one pixel is shortened. , and can sufficiently support high-speed imaging operations such as HDTV.

[Example] Next, an example will be described. FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a solid-state imaging device according to the present invention.

In the figure, 1-11 1-12...1-31
1-32. ... is a CMD (Charge Modula) that constitutes pixels arranged in a two-dimensional array.
tionDevice) type phototransistor, and 2 is a noise suppression circuit unit that suppresses fixed pattern noise included in the output signal of the CMD type phototransistor.

First, the imaging operation of the CMD type phototransistor will be explained. The imaging operation of the CMD type phototransistor constituting this pixel is divided into three operations: photoelectric conversion and charge accumulation operation, readout operation for outputting the photoelectric conversion result, and reset operation for discharging the accumulated charge. The second diagram shows the maximum potential distribution diagram for the gate of the CMD phototransistor and the potential distribution diagram between the source and drain for each operation mode.

Show to decoy. Photoelectric conversion! During charge accumulation, as shown by the solid line, a negative voltage that cuts off the phototransistor is applied to the gate electrode, and charges generated by photoelectric conversion are accumulated directly under the gate electrode. At the time of reading, as shown by the broken line, a potential is applied to the gate electrode such that the phototransistor changes from cutoff to conduction.

At this time, a current flows from the drain to the source corresponding to the charge accumulated directly under the gate electrode, and this current becomes an output signal. When discharging accumulated charges, the potential of the source is set to an appropriate negative potential, as shown by the dashed line, and the accumulated charges (holes) are discharged to the substrate side using the potential gradient.

The solid-state image sensor 3 is constructed by arranging such operating CMD type phototransistors in a two-dimensional array as described above, and 4 is a vertical shift register for selecting one row of the solid-state image sensor 3. , 5 is a first horizontal shift register for reading out the optical accumulation output signal of a selected row of pixels pixel by pixel. Further, 6 is a second horizontal shift register for resetting after reading out signals for each pixel in a selected row, and for reading out pixel signals immediately after reset. 7-L 7-2. . . . are horizontal selection switches driven by the first horizontal shift register 5, and 8-1. 8-2.・・・・・・、
9-1゜9-2. . . . are a reset switch and a horizontal selection switch for reading after reset, respectively, which are driven by the second horizontal shift register 6.

V,,V! , . . . are vertical shift registers 4 to 1.2. . . . is a drive pulse applied to the row selection line, and Hll, Hll . 7-2.・・・
Similarly, Htt is a driving pulse applied to Htt,
Hz□... is transmitted from the second horizontal shift register 6 to the reset switch 8-1. 8-2. ... and horizontal selection switch 9-L for reading after reset 9-
2. It is a driving pulse applied to...

Next, the operation of the solid-state imaging device configured as described above will be explained with reference to the timing chart of FIG. 3. By sequentially scanning the vertical shift register 4 and the first vertical shift register 5, output signals corresponding to the intensity of incident light appear sequentially on the output signal line 11 from each pixel forming the image sensor.

Here, the operation will be explained in more detail in the case where the read drive pulse shown in pulse (1) in FIG. 3 is applied to the vertical selection line in the first row. When the drive pulse train HIl, H120158,. is output from the first horizontal shift register 5, the horizontal selection switches 7-17-2.・・・・・・
are sequentially turned on, and the horizontal pixel column 1-IL 1-12. connected to the vertical selection line of the first row is turned on. . . . pixel output signals are sequentially read out to the output signal line 11.

The pixel output signal read out to the second output signal line 11 is amplified by the preamplifier 13-1 and becomes an output signal (2).

As shown in FIG. 3, this output signal vl includes an output signal component SII+ corresponding to the optical signal charge accumulated in each pixel.
In addition to S+z+..., non-uniform output offset component Nll+ for each pixel based on non-uniform characteristics of each pixel
Nl! +... are included respectively.

On the other hand, after the light accumulation output signal of the pixel 1-11 in the first column is output, the timing of the driving pulse H1□ that starts reading out the light accumulation output signal of the pixel 1-12 in the second column is the same. At this timing, the reset switch 8-1 in the first column is turned on by the drive pulse L+ from the second horizontal shift register 6, and the vertical signal line in the first column is set at a negative potential with respect to the gate electrode during readout. A reset voltage ■□ is applied such that the pixel 1-11 in the first row and first column immediately after the signal is read out is reset.

Next, the horizontal selection switch 9-1 for reading after setting the first column is driven by the drive pulse H,, which is applied to the second column of the second horizontal shift register 6 at the same timing as the horizontal selection drive pulse HI3 of the third column. is turned on, and the pixel signal of pixel 1-II in the first row and first column, for which the reset operation has just been completed, is read out to the output line 12, amplified by the preamplifier 13-2, and becomes the output signal 2. This output signal v2 is almost equal to the dark output signal of the pixel (normally the dark output includes an output component due to dark charge, so only that output component is different), and directly embodies the output non-uniformity of each pixel. Output offset component N 11. Only NIT is included.

Next, in the fixed pattern noise suppression circuit section 2, the phase of the output signal (1) is delayed by a delay element 2a to match the phase of the output signal (2) immediately after the corresponding same pixel is reset,
By performing subtraction in the differential circuit 2b, non-uniform output offset components Ni1 caused by non-uniform characteristics of each pixel are removed.
．． Nl21... is removed, and the output signal component Sl
It is possible to obtain a corrected output signal OUT with a good S/N ratio only for +, 5I21, . . . .

In this embodiment, a delay difference circuit is shown as the fixed pattern noise suppression circuit section, which delays the optical accumulation output signal (1) as described above and then takes the difference from the pixel signal (2) immediately after reset. In addition to this, for example, a double sample and hold circuit using two sample and hold circuits can also be used.

Further, in this embodiment, a CMD type phototransistor is used as a pixel, but the present invention is applicable to other amplification type image pickup devices, such as SIT type and AMI type.

It can also be applied to solid-state imaging devices using amplification type imaging elements such as BASIS type and FGA type, and essentially the same effect can be obtained although the reset implementation method is different.

Further, according to the present invention, the following effects can be additionally obtained. In other words, in the conventional in-element fixed pattern noise suppression method, the optical signal charge integration time from reset to readout differs between horizontal pixels by about one horizontal scanning period, and the integration time is particularly shortened by electronic shutter operation. In some cases, this difference in integration time appears as horizontal shading, which poses a problem in image quality. However, according to the present invention, since it is reset for each pixel, no difference in integration time occurs. The above problems are resolved.

Furthermore, according to the present invention, it is possible to reduce the reset level generation circuit required in the conventional vertical scanning circuit, and it is possible to reduce the scanning circuit area or chip area, which is advantageous in terms of yield and cost. becomes.

[Effects of the Invention] As described above based on the embodiments, the present invention eliminates the need for a reset transistor or IH memory for each pixel, reduces the scanning circuit area or chip area, and reduces costs. Accordingly, it is possible to provide a solid-state imaging device that can suppress fixed pattern noise. In addition, reading out the optical accumulation signal output, resetting, and reading out the pixel signal immediately after the reset can be performed at different timings.
A solid-state imaging device with fixed pattern noise suppressed can be obtained, which can sufficiently handle high-speed imaging operations with short pixel readout periods.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a solid-state imaging device according to the present invention, FIG. FIG. 3 is a timing chart for explaining the operation of the solid-state imaging device shown in FIG. In times 1-11. 1-12. ,...is a commercial
D-type phototransistor; 2 is a fixed pattern noise suppression circuit section; 3 is an image sensor; 4 is a vertical shift register; 5 is a first horizontal shift register; 6 is a second horizontal shift register; 7-L 7-2. ... is a horizontal selection switch,
8-L 8-2. ... is a reset switch, 9
-1°9-2. ... is the horizontal selection switch for reading after reset, IL 12 is the output line, 13-1.13-
2 indicates a preamplifier. Figure 2 (A) (B) Patent applicant: Olympus Optical Industry Co., Ltd. and one other source/drain

Claims (1)

[Scope of Claims] 1. In a solid-state imaging device equipped with a pixel array in which image sensors having an amplification function are arranged as pixels in a two-dimensional or one-dimensional array, an operation is performed to sequentially read out optical accumulation signals of each of the pixels. The first horizontal selection circuit is the same as the second horizontal selection circuit that performs a reset operation after reading out the optical accumulation signal by the first horizontal selection circuit of each pixel, and reads out the pixel signal immediately after the reset operation. A solid-state imaging device, comprising means for subtracting a pixel's light accumulation signal from a pixel signal immediately after a reset operation to reduce fixed pattern noise contained in the light accumulation signal of each pixel. 2. The image sensor constituting the pixel is composed of a phototransistor, and the reset operation by the second horizontal selection circuit is to set the source potential connected to the signal output line of the phototransistor to a negative potential compared to the gate potential. According to
2. The solid-state imaging device according to claim 1, wherein the photoelectric charge accumulated in the gate is discharged. 3. The first and second horizontal selection circuits are formed within the same element as the pixel array, and the fixed pattern noise reduction means is configured within the same element or as an external circuit. 3. The solid-state imaging device according to item 1 or 2.