JPH0452022B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a carrier wave regeneration circuit, input Ich and
Using Qch binary phase error information and binary phase error information whose phase is inverted in synchronization with this binary phase error information, ternary phase error information and inverted ternary phase error information are generated. By controlling the voltage controlled oscillator, the capture range is expanded while keeping the phase locked loop in a stable state.

[Industrial application field]

The present invention relates to an improvement in a carrier regeneration circuit, for example, a carrier regeneration circuit used in a demodulator of a digital multiplex radio device.

FIG. 4 shows a block diagram of a digital multiplex radio device demodulator. Hereinafter, the operation will be explained with reference to the diagram assuming that 64 orthogonal amplitude modulated waves are input.

First, the input 64 quadrature amplitude modulated waves (hereinafter referred to as
64QAM wave) is added to detectors 11 and 12, which also includes a voltage controlled oscillator (hereinafter referred to as 64QAM wave).
VOC omitted) 3 output wave or 90 degree phase shifter 1
Since the output wave phase-shifted by 90 degrees is added through 3, synchronous detection is performed to obtain Ich and Qch baseband signals.

This signal is converted into a digital signal by analog/digital converters (hereinafter abbreviated as A/D converter) 14 and 15 and sent to the outside, and the phase error signals E _i , _EQ and the digital signal are I
Signals I ₁ and Q ₁ that determine the quadrant on the -Q plane (hereinafter referred to as first path signals) are applied to a carrier recovery circuit (hereinafter abbreviated as CR circuit) 2.

Therefore, the CR circuit 2 uses these signals to generate a control signal and applies it to the VCO via a reduced pass filter (not shown), so the VCO
The frequency of the output wave (referred to as a regenerated carrier wave) is controlled so as to be synchronized with the radio modulated wave on the transmitting side.

At this time, a phase-locked loop (hereinafter referred to as PLL) consisting of a detector, A/D converter, CR circuit, and VCO is used so that correct data can be retrieved on the receiving side even if there is a large frequency fluctuation due to the unmodulated wave on the transmitting side. It is necessary to expand the capture range while maintaining a stable state.

[Conventional technology]

Fig. 5 is a block diagram of the conventional example, Fig. 6 is an explanatory diagram of the operation of Fig. 5, and Fig. 6a shows the first wave of the 64QAM wave.
Signal point constellation diagram in the 3rd quadrant, Figure 6b is the 5th
The level diagram of the figure is shown. The operation shown in FIG. 5 will be explained below with reference to FIG.

First, in Fig. 6a, when all the signal points rotate in the direction of the dotted arrow because the frequency of the unmodulated wave on the transmitting side fluctuates, when looking at the signal E, the level E _i
1 because it is above level E _Q , 0 because it is to the left of level I, 1 because it is above level I ₁ , level
Since it is to the right of Q ₁ , a pulse having information of 1 is applied to EX-OR gates 21 and 22 in FIG.

Therefore, the outputs 0 and 1 of the EX-OR gate are subtracted in an analog manner by the subtracter 23 to output -1 as shown in FIG. through
Variable capacitance dakiode D ₁ (hereinafter referred to as D ₁ ) in VCO3
), and the output of the subtracter 23 becomes 0.
The capacitance value of _D1 , that is, the oscillation frequency of the VCO is controlled so that

This control method is as shown in Fig. 6b.
Control VCO3 with a three-value control signal of 0 and -1, and
For example, lowers the oscillation frequency, 0 leaves it as is, -
1 indicates that it will be raised.

Further, C ₁ is a capacitor, R ₁ is a resistor, and R _V is a variable resistor.

[Problem that the invention seeks to solve]

Here, in order to be able to retrieve correct data on the receiving side even if there is a large frequency fluctuation due to the unmodulated wave on the transmitting side, it is necessary to widen the capture range of the PLL, but one method to do this is As is well known, the purpose of this is to increase the voltage of the control signal applied to the VCO, that is, the loop gain.

Therefore, if a DC amplifier is inserted between the loop filter 24 and the VCO 3, the voltage of the control signal will increase, but the frequency characteristics of the loop will change, increasing the possibility that the PLL will become unstable.

In other words, if you expand the capture range,
There is a problem that the stability of the PLL may decrease.

[Means for solving problems]

The above problems are solved by the carrier wave recovery circuit shown in FIG.

Here, 4 is a phase shift means that is synchronized with Ich or Qch binary phase error information and generates Ich or Qch binary phase error information with the phase reversed, and 5 is a phase shift means for generating Ich or Qch binary phase error information whose phase is inverted.
3 generated from Ich and Qch binary phase error information
This is a ternary phase error information generation means that sends out, as a control signal, ternary phase error information generated from the phase error information and binary phase error information of Ich and Qch whose phases are inverted.

[Effect]

The present invention generates ternary phase error information using Ich and Qch binary phase error information output from the phase shift means 4 and binary phase error information whose phase is inverted in synchronization with this error information. The ternary phase error information generated by the means 5 is applied to the voltage controlled oscillator 6.

At this time, the ternary phase error information and the inverted ternary phase error information change in opposite directions, so the ternary phase error information with double the amplitude is added to the voltage controlled oscillator, and the modulation sensitivity is compared to the conventional one. and increase.

Here, since the amplitude of the ternary phase error information is not increased using an amplifier, the capture range of the PLL can be expanded while maintaining a stable state.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. In addition, EX-OR gates 41, 42, D type flip-flop 4
3 and 44 are constituent parts of the phase shift means 4, differential amplifiers 51 and 52, and loop filters 53 and 54 are constituent parts of the ternary phase error information generation means 5. The operation shown in FIG. 2 will be explained below with reference to FIG.

First, Ich binary phase error information E _i , Q ₁ and Qch
The binary phase error information E _Q , Q ₁ of EX-OR gate 4
After being added to 1 and 42 and EX-ORed,
D type flip-flops (hereinafter abbreviated as D-FF) 43 and 44 are punched out by the clock CK.

The outputs of the Q terminals of the D-FFs 43 and 44 are added to the + and - terminals of the differential amplifier 51, and the outputs of the Q terminals are added to the + and - terminals of the differential amplifier 52, respectively, and the analog difference is removed. It will be done.

Therefore, when the information indicated by - in Fig. 3 is input to the differential amplifiers 51 and 52, -,
As shown in -, output information changed in the opposite direction is obtained, and [-]-[-], that is, 2, 0, -2 is added to both ends of the variable capacitance diode _D2 via the loop filters 53 and 54. However, this is twice as much as the conventional example.

In other words, while the PLL remains stable, the VCO
Since the voltage of the ternary phase error information, that is, the loop gain, can be doubled as soon as input to the input signal, the capture range is expanded.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
This has the effect of expanding the capture range while keeping the PLL stable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, FIG. 4 is a block diagram of a digital multiplex radio device demodulator, and FIG. The figure is a block diagram of a conventional example.
The figure shows an explanatory diagram of the operation of FIG. In the figure, 4 is a phase shift means, 5 is a ternary phase error information generating means, and 6 is a voltage controlled oscillator.

Claims (1)

[Claims] 1. In a carrier regeneration circuit that controls the oscillation frequency of the voltage controlled oscillator 6 with a control signal generated using Ich and Qch binary phase error information, the Ich or Qch binary phase error information synchronize,
A phase shift means 4 that generates binary phase error information of Ich or Qch whose phase is inverted, ternary phase error information generated from the binary phase error information of Ich and Qch, and Ich whose phase is inverted.
1. A carrier wave regeneration circuit comprising: a ternary phase error information generating means 5 for transmitting inverted ternary phase error information generated from Qch binary phase error information as the control signal.