JPH0452981Y2 - - Google Patents
Info
- Publication number
- JPH0452981Y2 JPH0452981Y2 JP17744587U JP17744587U JPH0452981Y2 JP H0452981 Y2 JPH0452981 Y2 JP H0452981Y2 JP 17744587 U JP17744587 U JP 17744587U JP 17744587 U JP17744587 U JP 17744587U JP H0452981 Y2 JPH0452981 Y2 JP H0452981Y2
- Authority
- JP
- Japan
- Prior art keywords
- internal electrodes
- multilayer ceramic
- ceramic dielectric
- ceramic capacitor
- dielectric sheets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は積層セラミツクコンデンサに関し、特
に内部電極の形状とその積層構成に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multilayer ceramic capacitor, and particularly to the shape of internal electrodes and the laminated structure thereof.
従来の積層セラミツクコンデンサは第2図aに
示すように、内部電極1aを形成したセラミツク
誘電体シート2aを、内部電極の向きが交互にな
るように180°回転させて複数枚積層させたのち、
その上下面に保護層となるセラミツク誘電体シー
ト21を複数枚積層して全体を熱圧着・一体化
し、セラミツクコンデンサ素体3aを形成し、し
かるのちセラミツクコンデンサ素体3aを焼成
し、その両端に外部電極4が被着形成されて得ら
れた。
As shown in FIG. 2a, a conventional multilayer ceramic capacitor is constructed by laminating a plurality of ceramic dielectric sheets 2a with internal electrodes 1a formed thereon by rotating them by 180 degrees so that the orientation of the internal electrodes is alternate.
A plurality of ceramic dielectric sheets 21 serving as protective layers are laminated on the upper and lower surfaces, and the whole is bonded and integrated by thermocompression to form a ceramic capacitor body 3a.Then, the ceramic capacitor body 3a is fired, and both ends of the ceramic dielectric sheet 21 are stacked. An external electrode 4 was deposited and formed.
上述した従来技術では、小容量の積層セラミツ
クコンデンサを設計したとき、内部電極1aの必
要有効枚数が数枚から1枚以下と少い場合、セラ
ミツク誘電体シート2aの厚みばらつき、あるい
はセラミツク誘電体シート2a複数枚積層したと
きの積層誤差により、設計容量を精度よく実現す
ることが困難となる。
In the above-mentioned conventional technology, when designing a small-capacity multilayer ceramic capacitor, if the required effective number of internal electrodes 1a is small, from several to one or less, variations in the thickness of the ceramic dielectric sheet 2a or the ceramic dielectric sheet Due to stacking errors when a plurality of 2a layers are stacked, it becomes difficult to accurately realize the designed capacity.
この問題を解決するため、単に内部電極1aの
面積を小さくする手段がとられており、内部電極
1aの必要枚数が増えるためにセラミツク誘電体
シート2aの厚みばらつきによる影響は軽減され
る。しかしセラミツク誘電体シート2aを複数枚
積層したときの積層誤差の影響が内部電極1aの
面積が小さくなるほど大きくなるため、結果とし
て設計容量を精度よく実現する困難さは変らない
という欠点があつた。 In order to solve this problem, a measure is taken to simply reduce the area of the internal electrodes 1a, and since the required number of internal electrodes 1a increases, the influence of variations in the thickness of the ceramic dielectric sheets 2a is reduced. However, the effect of stacking errors when a plurality of ceramic dielectric sheets 2a are stacked becomes greater as the area of the internal electrodes 1a becomes smaller, and as a result, it remains difficult to accurately realize the designed capacitance.
本考案の目的は、セラミツク誘電体シートの厚
みばらつきの影響、積層誤差の影響をなくし、小
容量品の設計精度を大幅に向上できる構造を有す
る積層セラミツクコンデンサを提供することにあ
る。 An object of the present invention is to provide a multilayer ceramic capacitor having a structure that eliminates the effects of thickness variations in ceramic dielectric sheets and stacking errors, and greatly improves the design accuracy of small-capacity products.
本考案による積層セラミツクコンデンサは、内
部電極の中央部が空白になるようドーナツ状に内
部電極を形成し、かつ直上下面の内部電極が一定
の割合で交互にずれて積層されることによつて直
上下面の内部電極の重なり部分が2ヶ所生ずるこ
とを特徴としている。
In the multilayer ceramic capacitor according to the present invention, the internal electrodes are formed in a donut shape so that the central part of the internal electrodes is blank, and the internal electrodes directly above and below are laminated with alternating shifts at a constant ratio. It is characterized by the fact that the internal electrodes on the bottom surface overlap in two places.
上記内部電極の形状とその積層構成が、本考案
の特徴である。 The shape of the internal electrode and its laminated structure are the features of the present invention.
以下本考案の実施例について図面を参照して説
明する。
Embodiments of the present invention will be described below with reference to the drawings.
第1図aは本考案による内部電極1を形成した
セラミツク誘電体シート2である。内部電極1は
ドーナツ状に中央部が空白になるよう形成されて
おり、かつ中心線A−A1線からずれて形成され
ている。 FIG. 1a shows a ceramic dielectric sheet 2 on which internal electrodes 1 according to the present invention are formed. The internal electrode 1 is formed in a donut shape so that the center part is blank, and is formed offset from the center line A-A1.
上記セラミツク誘電体シート2を内部電極1の
向きが逆になるよう交互に180°回転させて複数枚
積層したときの、直上下面2枚のセラミツク誘電
体シート2に形成された内部電極1の重なりの様
子をシート上面から透視で見たのが第1図cであ
る。上下面の内部電極1および11は第1図cの
BおよびCの2ヶ所で重なり合つている。この重
なり部分BおよびCの合計面積により積層セラミ
ツクコンデンサの容量が決定される。すなわち本
考案は、第1図cに示したように直上下面の内部
電極が2ヶ所で重なり合うよう内部電極1を形成
する。 When a plurality of ceramic dielectric sheets 2 are laminated by alternately rotating them by 180 degrees so that the directions of the internal electrodes 1 are reversed, the internal electrodes 1 formed on the two ceramic dielectric sheets 2 on the directly upper and lower surfaces overlap. Figure 1c shows a transparent view of the situation from the top of the sheet. Internal electrodes 1 and 11 on the upper and lower surfaces overlap at two locations B and C in FIG. 1c. The total area of the overlapping portions B and C determines the capacitance of the multilayer ceramic capacitor. That is, in the present invention, the internal electrode 1 is formed so that the internal electrodes on the upper and lower surfaces overlap at two places, as shown in FIG. 1c.
第1図aに示したセラミツク誘電体シート2を
内部電極1の向きが逆になるよう交互に180°回転
させて複数枚積層したのち、その上下面に第1図
bに示した保護層となるセラミツク誘電体シート
21を複数枚積層して、全体を熱圧着・一体化し
てセラミツクコンデンサ素体3を得る。しかるの
ち、これを焼成し、その両端に外部電極4を被着
形成して本考案の積層セラミツクコンデンサを得
る。第1図dは本考案の積層セラミツクコンデン
サを第1図aのA−A1線で切断した断面図で
あ。 After laminating a plurality of ceramic dielectric sheets 2 shown in FIG. 1a by rotating them alternately by 180 degrees so that the internal electrodes 1 are in the opposite direction, a protective layer shown in FIG. A ceramic capacitor body 3 is obtained by laminating a plurality of ceramic dielectric sheets 21, and then thermocompression bonding and integrating the whole. Thereafter, this is fired and external electrodes 4 are formed on both ends thereof to obtain the multilayer ceramic capacitor of the present invention. FIG. 1d is a sectional view of the multilayer ceramic capacitor of the present invention taken along line A-A1 in FIG. 1a.
〔考案の効果〕
上記実施例から、本考案の効果は以下にまとめ
られる。[Effects of the invention] From the above embodiments, the effects of the invention can be summarized as follows.
(1) 直上下面の内部電極の重なり部分の面積が小
さくでき、特に小容量の積層セラミツクコンデ
ンサを設計したとき、内部電極の必要枚数が多
くできるため、セラミツク誘電体シートの厚み
ばらつきの影響が軽減される。(1) The overlapping area of the internal electrodes on the top and bottom surfaces can be reduced, and especially when designing a small-capacity multilayer ceramic capacitor, the number of internal electrodes required can be increased, reducing the effect of thickness variations in the ceramic dielectric sheets. be done.
(2) 内部電極を形成したセラミツク誘電体シート
を積層するとき積層誤差が生じても、直上下面
の内部電極の重なり部分の面積は変わらないこ
とから積層誤差の影響がなくなる。(2) Even if a lamination error occurs when laminating the ceramic dielectric sheets on which the internal electrodes are formed, the area of the overlapping portion of the internal electrodes directly above and below does not change, so the influence of the lamination error is eliminated.
以上(1),(2)の効果から、本考案の積層セラミツ
クコンデンサは、特に小容量品の設計精度が従来
技術より向上する。 As a result of the above effects (1) and (2), the multilayer ceramic capacitor of the present invention has improved design accuracy, especially for small-capacity products, compared to the conventional technology.
第1図aは本考案の内部電極を形成したセラミ
ツク誘電体シートの上面図、第1図bは保護層と
なるセラミツク誘電体シートの上面図、第1図c
は第1図aのセラミツク誘電体シートを内部電極
の向きが逆になるよう180°回転させて2枚積層し
たときの内部電極の重なりの様子を上から透視し
て見た図、第1図dは本考案の積層セラミツクコ
ンデンサを第1図aのA−A1線で切断した断面
図、第2図aは従来技術の内部電極を形成したセ
ラミツク誘電体シートの上面図、第2図bは保護
層となるセラミツク誘電体シートの上面図、第2
図cは従来技術の積層セラミツクコンデンサを第
2図aのA−A1線で切断した断面図である。
1,11,21……内部電極、2,21、2a
……セラミツク誘電体シート、3,3a……セラ
ミツクコンデンサ素体、4……外部電極。
Fig. 1a is a top view of a ceramic dielectric sheet forming internal electrodes of the present invention, Fig. 1b is a top view of a ceramic dielectric sheet serving as a protective layer, and Fig. 1c
Figure 1 is a transparent view from above showing how the internal electrodes overlap when two ceramic dielectric sheets in Figure 1a are rotated 180 degrees so that the orientation of the internal electrodes is reversed and then stacked. d is a cross-sectional view of the multilayer ceramic capacitor of the present invention taken along line A-A1 in FIG. Top view of ceramic dielectric sheet serving as a protective layer, 2nd
FIG. c is a sectional view of a conventional multilayer ceramic capacitor taken along line A-A1 in FIG. 2a. 1, 11, 21...Internal electrode, 2, 21, 2a
. . . Ceramic dielectric sheet, 3, 3a . . . Ceramic capacitor body, 4 . . . External electrode.
Claims (1)
数枚交互に積層し、さらにその上下面に保護層と
なる誘電体シートを積層して一体化した積層セラ
ミツクコンデンサにおいて、内部電極の中央部が
空白になるようドーナツ状に内部電極を形成し、
かつ直上下面の内部電極が一定の割合で交互にず
れて積層されることによつて、直上下面の内部電
極の重なり部分が2ヶ所生ずることを特徴とする
積層セラツクコンデンサ。 In multilayer ceramic capacitors, which are made by laminating alternately multiple dielectric sheets with conductive internal electrodes, and further laminating dielectric sheets that serve as protective layers on the top and bottom surfaces, the central part of the internal electrodes is blank. Form the internal electrode in a donut shape so that
A multilayer ceramic capacitor characterized in that the internal electrodes on the immediately upper and lower surfaces are stacked alternately at a constant ratio, thereby creating two overlapping portions of the internal electrodes on the immediately upper and lower surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17744587U JPH0452981Y2 (en) | 1987-11-20 | 1987-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17744587U JPH0452981Y2 (en) | 1987-11-20 | 1987-11-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0180922U JPH0180922U (en) | 1989-05-30 |
| JPH0452981Y2 true JPH0452981Y2 (en) | 1992-12-14 |
Family
ID=31469109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17744587U Expired JPH0452981Y2 (en) | 1987-11-20 | 1987-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0452981Y2 (en) |
-
1987
- 1987-11-20 JP JP17744587U patent/JPH0452981Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0180922U (en) | 1989-05-30 |
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