JPH0453045Y2 - - Google Patents
Info
- Publication number
- JPH0453045Y2 JPH0453045Y2 JP1985171214U JP17121485U JPH0453045Y2 JP H0453045 Y2 JPH0453045 Y2 JP H0453045Y2 JP 1985171214 U JP1985171214 U JP 1985171214U JP 17121485 U JP17121485 U JP 17121485U JP H0453045 Y2 JPH0453045 Y2 JP H0453045Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- fet
- source
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
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- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案はSHF放送受信装置等に用いられるマ
イクロ波発振回路に関する。[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a microwave oscillation circuit used in SHF broadcast receivers and the like.
(ロ) 従来の技術
近年、放送衛星によるSHF放送が実用化され
つつあるが、SHF放送受信システムにおいては
12GHz帯のSHF波を受信するために次の様なマイ
クロ波発振回路が局部発振回路として用いられ
る。即ち、第３図は発振回路のパターン図、第４
図は高周波における等価回路図を示し、１はGa，
As（ガリウムヒ素）を用いたFET、２，３，４は
このFETのゲートＧ、ドレンインＤ及びソース
Ｓに夫々接続されたストリツプ線路、５は前記ス
トリツプ線路２及び３に結合され共振回路を形成
する誘電体共振器であり、これにより発振周波数
が制御され、発振出力はソースＳから取出されて
次段の混合回路（図示省略）へ印加される。尚
C1はドレンイＤを高周波的に接地するキヤパシ
タC2は直流カツト要のキヤパシタ、RLは負荷抵
抗、Rg，Rdは終端抵抗である。また、Zg，Zdは
ストリツプ線路２，３の夫々特性インピーダンス
である。(b) Conventional technology In recent years, SHF broadcasting using broadcasting satellites has been put into practical use, but in SHF broadcasting receiving systems,
In order to receive SHF waves in the 12GHz band, the following microwave oscillation circuit is used as a local oscillation circuit. That is, Fig. 3 is a pattern diagram of the oscillation circuit, and Fig. 4 is a pattern diagram of the oscillation circuit.
The figure shows an equivalent circuit diagram at high frequency, where 1 is Ga,
A FET using As (gallium arsenide), 2, 3, and 4 are strip lines connected to the gate G, drain in D, and source S of this FET, and 5 is coupled to the strip lines 2 and 3 to form a resonant circuit. The oscillation frequency is controlled by this dielectric resonator, and the oscillation output is taken out from the source S and applied to the next stage mixing circuit (not shown). still
C1 is a capacitor that grounds the drain D at high frequency; C2 is a capacitor required for DC cut; RL is a load resistance; Rg and Rd are terminating resistances. Further, Zg and Zd are characteristic impedances of the strip lines 2 and 3, respectively.
更に低周波数での等価回路は第５図の様になり
セルフバイアス用の抵抗RSGによりゲート電圧
をソース電圧に対して負のバイアスとされてい
る。尚、この様なマイクロ波発振回路は例えば特
開昭59−224904号公報に示されている。 Furthermore, the equivalent circuit at a low frequency is as shown in FIG. 5, where the gate voltage is negatively biased with respect to the source voltage by the self-biasing resistor RSG. Incidentally, such a microwave oscillation circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-224904.
上述のマイクロ波発振回路において、その発振
周波数は、周囲温度変化に起因する種々要因によ
り変動する。例えば、温度変化に依存するFET
のドレイン電流IDの変化によりソース・ゲート
間電圧VSGが変化し、発振周波数が変動する。 In the microwave oscillation circuit described above, the oscillation frequency thereof fluctuates due to various factors caused by changes in ambient temperature. For example, FETs that depend on temperature changes
As the drain current ID changes, the source-gate voltage VSG changes, causing the oscillation frequency to fluctuate.
(ハ) 考案が解決しようとする問題点
本考案は上述の点に鑑み為されたものであり、
温度変化によりFETのドレイン電流が変化して
も発振周波数の変動が少ないマイクロ波発振回路
を提供するものである。(c) Problems that the invention aims to solve This invention was created in view of the above points,
The present invention provides a microwave oscillation circuit in which the oscillation frequency does not fluctuate much even if the drain current of the FET changes due to temperature changes.
(ニ) 問題点を解決するための手段
本考案はFETのソースに定電圧回路を接続し
てなるマイクロ波発振回路である。(d) Means for solving the problem The present invention is a microwave oscillation circuit formed by connecting a constant voltage circuit to the source of an FET.
(ホ) 作用
上述の手段によりFETのソース電圧が常に一
定となりソース・ゲート間電圧（VSG）が固定
される。(e) Effect By the means described above, the source voltage of the FET is always constant, and the source-gate voltage (VSG) is fixed.
(ヘ) 実施例
以下図面に従い本考案の一実施例を説明する。
まず、第１図は本考案の原理的な回路図を示し、
FET１のソースＳには定電圧回路６が接続され
ている。従つて、ソース電圧が常に一定となり、
抵抗RSGには定電流が流れるためソース・ゲー
ト間電圧VSGが固定され、温度変化による発振
周波数の変動が緩和される。(F) Embodiment An embodiment of the present invention will be described below with reference to the drawings.
First, Figure 1 shows the basic circuit diagram of the present invention,
A constant voltage circuit 6 is connected to the source S of the FET 1. Therefore, the source voltage is always constant,
Since a constant current flows through the resistor RSG, the source-gate voltage VSG is fixed, and fluctuations in the oscillation frequency due to temperature changes are alleviated.
次に第２図は定電圧回路の具体的回路図を示
し、FET１のドレインＤとソースＳには夫々ト
ランジスタTrのコレクタ及びエミツタが接続さ
れ、ベースにはダイオードD1が接続されている。
また、コレクタとベース間は抵抗R1を介して接
続されている。第２図においてトランジスタTr
のベース電位はベースに接続されたダイオード
D1の順方向降下電圧（一定）となる。そして、
エミツタ電圧即ち、抵抗RSGの端子電圧は前記ベ
ース電圧より一定電圧低い電圧となるため、抵抗
RSGの端子電圧も常に一定となる。よつて、これ
らは低電圧回路６として動作し、FET１のソー
ス電圧を一定とする。 Next, FIG. 2 shows a specific circuit diagram of a constant voltage circuit, in which the collector and emitter of a transistor T r are connected to the drain D and source S of the FET 1, respectively, and the diode D 1 is connected to the base.
Furthermore, the collector and base are connected via a resistor R1 . In Figure 2, the transistor T r
The base potential of is the diode connected to the base
This is the forward voltage drop (constant) of D1. and,
The emitter voltage, that is, the terminal voltage of the resistor RSG is a certain voltage lower than the base voltage, so the resistor
The terminal voltage of RSG is also always constant. Therefore, these operate as a low voltage circuit 6 and keep the source voltage of the FET 1 constant.
(ト) 考案の効果
上述の如く本考案に依れば、温度変化によるソ
ース・ゲート間電圧の変動を無くなるため発振周
波数の変動が抑えられる。(g) Effects of the invention As described above, according to the invention, fluctuations in the source-gate voltage due to temperature changes are eliminated, so fluctuations in the oscillation frequency can be suppressed.
第１図は本考案のマイクロ波発振回路の原理
図、第２図は第１図の具体的実施例を示す回路
図、第３図は従来のマイクロ波発振回路のパター
ン図、第４図は第３図の高周波における等価回路
図、第５図は第３図の低周波における等価回路図
である。
１……FET、Ｇ……ゲート、Ｄ……ドレイン、
Ｓ……ソース、２，３，４……ストリツプ線路、
５……誘電体共振器、６……定電圧回路。
Figure 1 is a principle diagram of the microwave oscillation circuit of the present invention, Figure 2 is a circuit diagram showing a specific embodiment of Figure 1, Figure 3 is a pattern diagram of a conventional microwave oscillation circuit, and Figure 4 is FIG. 3 is an equivalent circuit diagram at a high frequency, and FIG. 5 is an equivalent circuit diagram at a low frequency of FIG. 1...FET, G...gate, D...drain,
S... Source, 2, 3, 4... Strip line,
5...Dielectric resonator, 6... Constant voltage circuit.
Claims (1)
記FETのゲートに正帰還をかけてなるマイクロ
波発振回路において、 前記FETのソースに温度変化によらずソース、
ゲート間電圧（VSG）を一定にする定電圧回路
を接続してなるマイクロ波発振回路。[Claims for Utility Model Registration] In a microwave oscillator circuit in which positive feedback is applied from the drain of an FET to the gate of the FET via a dielectric resonator, the source of the FET is independent of temperature changes;
A microwave oscillation circuit that is connected to a constant voltage circuit that keeps the gate-to-gate voltage (VSG) constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985171214U JPH0453045Y2 (en) | 1985-11-07 | 1985-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985171214U JPH0453045Y2 (en) | 1985-11-07 | 1985-11-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6280415U JPS6280415U (en) | 1987-05-22 |
| JPH0453045Y2 true JPH0453045Y2 (en) | 1992-12-14 |
Family
ID=31106637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985171214U Expired JPH0453045Y2 (en) | 1985-11-07 | 1985-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453045Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50117750U (en) * | 1974-03-11 | 1975-09-26 |
-
1985
- 1985-11-07 JP JP1985171214U patent/JPH0453045Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6280415U (en) | 1987-05-22 |
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