JPH0454098U - - Google Patents
Info
- Publication number
- JPH0454098U JPH0454098U JP9439990U JP9439990U JPH0454098U JP H0454098 U JPH0454098 U JP H0454098U JP 9439990 U JP9439990 U JP 9439990U JP 9439990 U JP9439990 U JP 9439990U JP H0454098 U JPH0454098 U JP H0454098U
- Authority
- JP
- Japan
- Prior art keywords
- sense amplifier
- memory cell
- cell array
- column
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 230000008929 regeneration Effects 0.000 claims 1
- 238000011069 regeneration method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Dram (AREA)
Description
第１図は本考案の一実施例のダイナミツク型半
導体記憶装置のブロツク図、第２図は第１図のメ
モリセル部およびセンスアンプ部を１セルに限り
示す図、第３図は本実施例のデータ転送サイクル
を示す図である。
１０１……タイミングジエネレータ、１０２…
…アドレス入力バツフア、１０３……ロウデコー
ダ、１０４……ロウセンスアンプ、１０５……カ
ラムデコーダ、１０６……カラムセンスアンプ、
１０７……メモリセルアレイ、１０８……トラン
スフアンゲート、１０９……シリアルデータレジ
スタ、１１０……アドレスカウンタ、１１１……
シリアルデータセレクタ、１１２……入出力バツ
フア、１１３……シリアル出力バツフア、１１４
……メモリセル、１１５，１１６……オアゲート
。
FIG. 1 is a block diagram of a dynamic semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing only one cell of the memory cell section and sense amplifier section of FIG. 1, and FIG. 3 is a diagram of the present embodiment. FIG. 2 is a diagram showing a data transfer cycle of FIG. 101...timing generator, 102...
... Address input buffer, 103 ... Row decoder, 104 ... Row sense amplifier, 105 ... Column decoder, 106 ... Column sense amplifier,
107...Memory cell array, 108...Transfer gate, 109...Serial data register, 110...Address counter, 111...
Serial data selector, 112...Input/output buffer, 113...Serial output buffer, 114
...Memory cell, 115,116...OR gate.
Claims (1)
セルアレイと、シリアルアクセス可能なシリアル
データレジスタを有するダイナミツク型半導体記
憶装置において、 前記メモリセルアレイに、カラム方向からデー
タの判定、増幅、再書込みが行なえるカラムセン
スアンプと、ロウセンスアンプとカラムセンスア
ンプの入力データの論理和をとり、出力をシリア
ルデータレジスタへ出力するオアゲートを有する
ことを特徴とするダイナミツク型半導体記憶装置
。[Claims for Utility Model Registration] In a dynamic semiconductor memory device having a randomly accessible dynamic memory cell array and a serially accessible serial data register, the memory cell array is provided with data determination, amplification, and regeneration from a column direction. 1. A dynamic semiconductor memory device comprising a column sense amplifier that can perform writing, and an OR gate that logically ORs input data of the row sense amplifier and the column sense amplifier and outputs the output to a serial data register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9439990U JPH0454098U (en) | 1990-09-07 | 1990-09-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9439990U JPH0454098U (en) | 1990-09-07 | 1990-09-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0454098U true JPH0454098U (en) | 1992-05-08 |
Family
ID=31832307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9439990U Pending JPH0454098U (en) | 1990-09-07 | 1990-09-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0454098U (en) |
-
1990
- 1990-09-07 JP JP9439990U patent/JPH0454098U/ja active Pending
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