JPH0265295U - - Google Patents

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Publication number
JPH0265295U
JPH0265295U JP14406988U JP14406988U JPH0265295U JP H0265295 U JPH0265295 U JP H0265295U JP 14406988 U JP14406988 U JP 14406988U JP 14406988 U JP14406988 U JP 14406988U JP H0265295 U JPH0265295 U JP H0265295U
Authority
JP
Japan
Prior art keywords
memory
sense amplifier
memory cells
selector
dummy cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14406988U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14406988U priority Critical patent/JPH0265295U/ja
Publication of JPH0265295U publication Critical patent/JPH0265295U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図、第2
図は第1図のセンス・アンプ・ダミー・セル列の
単位セルの回路図である。 101……ライト・コントロール、102……
DINバツフア、103……ライト・セレクタ、
104……スタテイツク・セル・アレイ、105
……リード・セレクタ、106……センス・アン
プ・ダミー・セル列、107……ライト・カラム
・セレクタ、108……ダイナミツク・メモリ・
セル・アレイ、109……ライト・ロウ・セレク
タ、110……リード・ロウ・セレクタ、111
……リード・カラム・セレクタ、112……リー
ド・コントロール、113……センス・アンプ・
DOUTバツフア。
Fig. 1 is a block diagram of an embodiment of the present invention;
FIG. 1 is a circuit diagram of a unit cell of the sense amplifier dummy cell column shown in FIG. 101...Light control, 102...
DIN buffer, 103...Light selector,
104...Static cell array, 105
... Read selector, 106 ... Sense amplifier dummy cell column, 107 ... Write column selector, 108 ... Dynamic memory
Cell array, 109...Write row selector, 110...Read row selector, 111
... Read column selector, 112 ... Read control, 113 ... Sense amplifier
DOUT but hua.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ダイナミツク形バイポート・メモリ・セルを有
するFIFOメモリであるライン・メモリにおい
て、そのメモリセルをリフレツシユするセンスア
ンプ及びダミーセルを有することを特徴とする半
導体記憶装置。
1. A semiconductor memory device characterized in that a line memory which is a FIFO memory having dynamic biport memory cells includes a sense amplifier and a dummy cell for refreshing the memory cells.
JP14406988U 1988-11-02 1988-11-02 Pending JPH0265295U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14406988U JPH0265295U (en) 1988-11-02 1988-11-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14406988U JPH0265295U (en) 1988-11-02 1988-11-02

Publications (1)

Publication Number Publication Date
JPH0265295U true JPH0265295U (en) 1990-05-16

Family

ID=31411450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14406988U Pending JPH0265295U (en) 1988-11-02 1988-11-02

Country Status (1)

Country Link
JP (1) JPH0265295U (en)

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