JPH0454531A - Program reading circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a program read circuit that generates a read address for a program memory.

[Prior Art] Conventionally, a programmable controller stores in a data memory each signal indicating the on/off level of a large number of contacts transmitted from a device to be controlled, and then performs sequence calculation based on the on/off level of these contact signals. I do. The result of this sequence calculation is stored in the data memory as a contact signal indicating the on/off level of the contact of the device to be controlled, and then transmitted to the device to be controlled.

A sequence program that defines the contents of the sequence operation is stored in advance in a program memory in the order of execution in units of sequence instructions, and when an operation is executed, the sequence instructions to be operated are successively read out from the program memory by addressing the program counter.

Among the sequence instructions, there are instructions (referred to as application instructions) that require a program instruction to be skipped over several steps if the level of a specific contact signal is at a specified level, for example, on.

In such a case, in the conventional circuit, the reading address of the jump destination is set by interrupting the reading of the program memory and idling the program counter. For this reason, in the conventional circuit, sequence calculations had to wait for the idle time, which was an obstacle to shortening the calculation processing time.

For this reason, the applicant of the present application has proposed a program reading circuit that eliminates the need to perform the above-mentioned idle processing by setting the initial setting value of the program counter to the jump destination reading address.

[Problem to be Solved by the Invention] However, in this proposal, it is not possible to use a program counter with a fixed initial setting value, which is commonly used in the past, due to the reset signal, so sequence calculations such as system startup At the beginning of each
There is still room for improvement in that the initial setting values of multiple bits must be input and set in the program counter.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide a program reading circuit that can perform read address jump processing without performing idle processing even when using a program counter with a fixed initial setting value. It's about doing.

[Means for Solving the Problems 1] In order to achieve such an object, the present invention provides a program reading circuit that sequentially reads out program instructions to be operated on from a program memory by addressing,
a counting means that takes the reading start position of the program memory as an initial setting value and continuously updates a count value by "1" each time the operation is executed; and an address jump number for a jump instruction among the program instructions; is written in the jump instruction in advance and detects that the program instruction read from the program memory is the jump instruction; and when the jump instruction is detected by the jump instruction detection means; a first addition means for cumulatively adding the number of address jumps indicated by the jump instruction; a count result of the counting means and a cumulative result of the first addition means; and the addition result is used as a read address for the program memory. and a second addition means for outputting the output.

[Function] In the present invention, when jump processing is performed multiple times from a certain address, the read address that is continuously updated thereafter is always equal to the number of address jumps from the read address that is continuously updated without performing jump processing. Focusing on the fact that there is a certain difference, in the present invention, each time a jump process is detected, the read address is added to the first adder and It is created by the second addition means.

[Embodiment 1] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a calculation section of a program controller to which the present invention is applied.

In FIG. 1, this circuit is comprised of a program memory 1, a data memory 2, and a bit sequence calculator 3.

In the bit sequence processing, the program counter 5 outputs a read address to the program memory 1, and the sequence command read from the program memory 1 is latched into the instruction register 4. The instruction register 4 conveys the processing contents of the instruction to each processing block in the sequence calculator 3.
When the instruction is to calculate contact information, the instruction register 4 outputs a read address to the data memory 2 and reads the stored data from the data memory 2.

Necessary bit information in the read data is extracted by the multiplexer 11, arithmetic is performed by the bit arithmetic unit 1o, and the result is stored in the arithmetic register 9.

On the other hand, if the instruction to read from the program memory 1 is a coil instruction that instructs data output, the instruction register 4 outputs the read address of the data to be output to the data memory 2, and reads the data from the data memory 2. The coil instruction processing circuit 12 further replaces only the bits necessary for the coil instruction processing circuit in the read data with the data in the bit operation register 9, and writes the data into the output data area in the data memory again.

As shown in FIG. 2, the program counter 5 includes a counter 6, a first adder 7. Second adder8. AND circuit 6-2.
7-1 and an OR circuit 6-1. The counter 6 (counting means) is for counting the number of times the read address is output from the second adder (second addition means) 8 to the program memory 1, and is created by OR output of multiple bits of the read address. The clock is input in synchronization with the synchronous clock for sequence calculation.

The first adder (first addition means) 7 cumulatively adds the address jump number each time the address jump number is output from the instruction register 4.

A second adder (second addition means) 8 adds the count value of the counter 6 and the cumulative result of the first adder 7, and outputs the addition result as a read address to the program memory 1.

The AND circuit 7-1 outputs the address jump number output from the instruction register 4 to the first adder 7 when the ON jump instruction signal is input from the operation register 9.

The format of the sequence instruction used in this example is
As shown in the figure.

In FIG. 3, an application instruction in a sequence instruction is an identification instruction code area 13. Bit area 14 indicating whether there is a jump. Bit area 15 indicating jump conditions. Address jump number area 1 with jump
6. The bit information in the data memory is divided into address areas 17, and predetermined information is stored in each area.

Next, the operation related to the present invention in the circuit shown in FIG. 1 will be explained.

As shown in FIG. 4, it is assumed that an application instruction including a conditional jump instruction is stored at address "3" of the program memory 1.

In FIG. 1, when the system is started up, each circuit becomes operable by a reset signal generated by a reset signal generation circuit (not shown).

At this time, the counter 6 and the first adder 7 in FIG. Address "1" is output to the program memory.

As a result, the sequence instruction stored at address "1" is output to the instruction register 4.

Since this sequence instruction is a normal instruction, data indicating the number of address jumps is not output from the instruction register 4 (the number of address jumps "0" is output).

In response to this normal instruction, the operation data to be operated on is read from the data memory 2, and the bit operation unit IO performs a sequence operation as described above. In addition, the bit operator l
Since O is also not an execution of an application instruction, no jump instruction signal is output to the arithmetic register 9, and the jump instruction signal for the program counter 5 of the arithmetic register 9 is held at the off level.

On the other hand, in the program counter shown in FIG.
Address “1” while O sequence operation is being performed.
However, when a synchronous clock indicating the calculation timing of the next step is input, the OR circuit 6-
1. A clock signal generated from the read address and the synchronization clock is input to the counter 6 via the AND circuit 6-2, and the count value of the counter 6 is updated from "1" to "2".

Since “0” is input as the address jump number to the first adder 7, the output of the first adder 7 is °゛0”, and as a result, the addition result of the second adder 8 is “2”. +“0”
= "2", and the read address for the program memory 1 is updated from "1" to "2".

Therefore, the sequence instruction to be operated on is read from address "2" of program memory 1.

Thereafter, following the same procedure, counter 6 will be set to “
3”, the application instruction (
(see FIG. 4) is read out.

When this application instruction is stored in the instruction register 4 of FIG. 1, the number of address jumps is sent to the program counter 5 based on the conditional jump presence information (see FIG. 3) in the application instruction. At this time, the instruction register operates as jump instruction detection means.

In addition, the data to be determined read from the data memory 2 (
A determination is made in the bit arithmetic unit IO as to whether the contact information (contact information) satisfies any of the on/off jump conditions.

If the result of this determination is to jump, for example, an on signal indicating the result of this determination is sent to the program counter 5 via the arithmetic register 9.

This ON signal opens the gate of the AND circuit 7-1 in the program counter 5 of FIG. The first adder 7 adds the current cumulative result "O" and the input "3" and transfers the addition result "3" to the second adder 8.
Output to.

The second adder 8 adds the current count value "3" of the counter 6 to the first adder 8.
The cumulative value “3” of adder 7 is added, and the addition result is “6”
is output to the program memory 11 at the next synchronous clock. Therefore, the program counter 5 can set the jump destination address in one clock cycle without running idly as in the conventional case.

Further, if the judgment result of the jump condition of the application instruction is no jump, an off signal is output from the arithmetic register 9 in FIG. 1, so the gate of the AND circuit 7-1 in FIG. 2 does not open, and therefore, The cumulative result of the first adder 7 remains "0". Therefore, the addition result of the second adder 8 is “3”.
" is held. Next, when the count value of the counter 6 is updated from "3" to "4", the output of the second adder 8 is also "3".
" is updated to "4". In this way, when the address is not jumped, the sequence instructions attached to the application instructions are sequentially read out as shown in FIG.

In this way, if the sequence instruction is read from the program memory 1 and the address is to be jumped by, for example, 4 steps by the second application instruction, the first counter 7
adds “4” to the current cumulative value “3” to make the cumulative value “7”
”.

The second adder 8 adds the cumulative value "7" to the count value of the counter 6 to create a read address for the program memory 1 to be skipped.

As described above, even when address jump processing is performed multiple times, the address processing can be performed in one step each time. Further, the counter 6 can perform counting continuously without interrupting counting.

In this embodiment, the program memory 1 in FIG.
Although the signal system of read/write signals for the data memory 2 and other control signals is omitted, it is sufficient to correspond to the timing of the address signal.

In addition to this embodiment, the following examples are given.

l) Although jump processing for application instructions has been described in this embodiment, it goes without saying that the present invention can also be applied to simple jump processing, such as jump processing for transitioning to a subroutine program or loop processing. .

Note that if the jump destination address has a smaller address jump number than the current address, a negative value will be used for the address jump number.

2) In this embodiment, a jump instruction (applied instruction) is detected using an instruction register, but it is also possible to use a code identification circuit such as a decoder.

[Effect of the Invention 1] As explained above, according to the present invention, jump processing is possible with one operation clock even if a counting means (counter) with a fixed initial value is used. The calculation time is shorter than that of a circuit. Further, by using a counting means with a fixed initial value, only a 1-bit reset signal can be used for initial processing such as power-on, and the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the embodiment of the present invention. FIG. 2 is a block diagram showing the circuit configuration of the program counter 5 in FIG. Explanatory Diagram FIG. 4 is an explanatory diagram showing the arrangement order of program instructions in the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Program memory, 2...Data memory, 3...Pit sequence arithmetic unit, 4...Instruction register, 5...Program counter, 6...Counter, 6-1...OR Circuit, 6-2.7-1...AND circuit, 7...First adder, 8...Second adder, 9...Arithmetic register, lO...Bit arithmetic unit, II. ...Multiplexer.

Claims (1)

[Scope of Claims] 1) A program readout circuit that sequentially reads out program instructions to be operated on from a program memory by addressing, wherein the readout start position of the program memory is set as an initial setting value, and the execution of the operation is performed. counting means for continuously updating the count value by "1" for each time; and for a jump instruction among the program instructions, the number of address jumps is written in advance in the jump instruction;
jump detection means for detecting that the program instruction read from the program memory is the jump instruction, and when the jump instruction is detected by the jump instruction detection means, cumulatively detecting the number of address jumps indicated by the jump instruction; and a second addition means for adding the counting result of the counting means and the cumulative result of the first adding means and outputting the addition result as a read address for the program memory. A program readout circuit featuring: