JPH0454657A - Data transfer device - Google Patents

Abstract

PURPOSE:To improve the performance by constituting the device so that at the time of retry operation, the contents of a retry storage element are retransferred to an output FIFO, and an input memory can receive the next data from an information processor of a transfer origin immediately after transferring the data to the output FIFO. CONSTITUTION:When a retry request is generated from an information processor of a transfer origin after a data transfer is finished, a read pulse is supplied to an output enable signal - OE1 of a storage element 1. Also, a write pulse is supplied to a write enable signal - WE61 of an output FIFO 61. As a result, the data accumulated in the storage element 1 is outputted to a data bus 4, and transferred to the output FIFO 61. At every single data transfer, an address register is subjected to plus '1', and a range register 34 is subjected to minus '1'. A single DMA transfer is executed until the contents of the register becomes '1', and at the timing by which the contents of the register 34 become '0' from '1', a start instruction FF 31 is reset and the DMA transfer is completed. In such a way, the data which becomes the cause for generating the retry request is reloaded to the output FIFO 61 from the storage element 1.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the data transfer apparatus of an information processing apparatus.

In particular, after data transfer is completed, IJ from the destination device)
This relates to IJ) lie processing when a lie request is made.

〔overview〕

The present invention provides a data transfer device with a storage element for IJ) line having a capacity greater than the total capacity of the output FIFO, and writes the same data into this storage element at the same time when data is transferred from the input memory to the output FIFO. By retransferring the contents of this memory element to the output FIFO during retry operation, the input memory can immediately retrieve the next data from the source information processing device after transmitting the data to the output FIFO. This improves performance and improves the recovery rate from intermittent failures.

[Conventional technology]

Conventionally, a data transfer device has a one-way try method in which, after transferring data from an output FIFO to a destination information processing device, if a try request is notified from the information processing device, data is transferred from an input memory to an output FIFO. After retransferring the data to the destination information processing device.

The other, simpler method is to transfer data from the input memory to the output FIFO without retransferring the data from the input memory to the output FIFO.
Some systems retransferred data from O to the destination information processing device.

[Problem to be solved by the invention]

However, in such conventional data transfer devices, the other try method is a remedy for intermittent failures that occur before data is transferred from the input memory to the output FIFO, such as intermittent failures that occur when writing to the output FIFO. is not done at all.

Therefore, even if the data is retransferred to the destination information processing device, the recovery rate is quite low. This is because the data stored in the output FIFO has a factor that causes a retry request, and to remove this, the output FIFO
This is because it is necessary to reload data into the FO. Generally, when an intermittent failure occurs, there is a high probability that the system will recover by reloading.

In addition, in the one-way try method, since there is a possibility of retransfer, it is important to note that after data is transferred from the output FIFO to the destination information processing device, an IJ) write request is not notified from the destination information processing device. Since the contents of the input memory cannot be rewritten until confirmation is made, the information processing device that is the data transfer source must be kept waiting. However, in general, the presence or absence of a try request can be confirmed from the destination information processing device after a considerable delay after data transfer from the output FIFO to the destination information processing device is completed. Therefore, making the transfer source information processing device wait during this time has the drawback of significantly reducing performance.

The present invention solves the above-mentioned drawbacks, and the input memory can immediately receive the next data from the source information processing device after transferring data to the output FIFO, thereby improving performance and recovering from intermittent failures. An object of the present invention is to provide a data transfer device that can improve the transfer rate.

[Means to solve the problem]

The present invention includes an input memory for storing input data, temporarily storing the contents of the input memory and outputting it to an external device,
Multiple output FIFOs that re-output their contents based on retry requests, the above input memory and the above output FIFO○
access control means for controlling access to the input memory, and the access control means controls the input memory and one of the plurality of output FIFOs to read the contents of the input memory and write the contents to the one output FIFO. A data transfer device including a write control means for temporarily storing the contents of the input memory, wherein the access control means controls the storage means and the output FIFO based on the retry request to write the contents of the input memory. The present invention is characterized in that it includes rewrite control means for reading out the corresponding contents and writing them into the output FIFO as the contents to be output again.

Further, in the present invention, the storage means is connected to the plurality of output FIFs.
The storage element may include a storage element having a capacity greater than or equal to the total capacity of O, and the storage element may include areas respectively corresponding to the plurality of output FIFOs.

Furthermore, the storage means includes simultaneous write control means that controls the storage element simultaneously with the write control of the write control means to write the contents of the input memory into the areas corresponding to the two output FIFOs. be able to.

[Effect]

The storage means temporarily stores the contents of the input memory.

The write control means again controls the storage means and the output FIFO based on the try request to read out the corresponding contents of the storage means and write them into the output FIFO as the contents to be output again.

Further, the storage means includes a storage element having a capacity greater than or equal to the total capacity of the plurality of output FIFOs, the storage element includes areas respectively corresponding to the plurality of output FIFOs, and the storage means includes a write control means by the simultaneous write control means. An output FI that controls the writing of the input memory by controlling the storage element at the same time as the writing control of the input memory.
Write to the area corresponding to FO.

As described above, the input memory can immediately receive the next data from the information processing device that is the transfer source after transferring data to the output FIFO, thereby improving performance and improving the recovery rate from intermittent failures.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a data transfer device according to an embodiment of the present invention. In FIG. 1, the data transfer device includes an input memory 2 that stores input data, and multiple outputs that temporarily store the contents of the input memory 2 and output them to an external device, and output the contents again based on a retry request. FIF060.61
．． 62.63, input memory 2 and output FIF060
．． The access control means includes a control processor 7, a DMA controller 3, and a memory control circuit 5 as access control means for controlling access to the input memory 2 and one of the plurality of output FIFs.
A control processor 7, a flip-flop 31 for start instruction, an address register 33, 35, a range register 34, and a memory controller are used as write control means for controlling the input memory 2 to read the contents of the input memory 2 and write them to this one output FIFO. Includes circuit 5.

Here, a feature of the present invention is that the access control means is provided with a storage means for temporarily storing the contents of the input memory 2, and the access control means is connected to the storage means and the output FI based on a try request.
Control F060.61.62.63 to read out the corresponding contents of the storage means and output FIF060.61.62
．． The control processor 7, the start instruction flip-flop 31, the selection flip-flop 32, the address register 33, 35, the range register 34, and the memory control circuit 5 are included as a re-write control means for writing the content to be re-outputted to the 63. It is in.

Further, the storage means includes a plurality of output FIFOs 60, 61,
62 and 63, including a storage element 1 having a capacity greater than the total capacity of 62 and 63;
Storage element l has multiple outputs F I F 060.61.6
2.63, respectively.

Further, the storage means registers an address register as a simultaneous write control means for controlling the storage element 1 and writing the contents of the input memory 2 into an area corresponding to one output FIFO simultaneously with the write control of the write control means. Contains 35.

The operation of the data transfer device having such a configuration will be explained. FIG. 2 is a diagram showing output FIFO allocation to storage elements of the data transfer device of the present invention.

FIG. 3 is a block diagram of the memory control circuit of the data transfer device of the present invention. FIG. 4 is a time chart of normal data transfer by the data transfer device of the present invention. FIG. 5 is a time chart of data transfer when trying to connect the data transfer apparatus of the present invention.

Table 1 is a table showing the truth values of the decoder of the data transfer device of the present invention. Table 2 is a table showing the operations of the input memory, storage element, and output FMFO of the data transfer device of the present invention.

(See the margins of this page below) Table 1 Decoder truth table Table 2 Operation table of input memory, storage element, and output FIFO In Figure 1, data transferred from the source information processing device to this data transfer device Input memory 2 that stores
It is assumed that four output FIFs 060 to 63, which store data to be transferred from this device to a destination information processing device, are connected via a data bus 4, each having a storage capacity of IK bytes.

DM A (Direct Memory Access
ss):] The controller 3 includes a start instruction flip-flop 31 for instructing the start of a DMA transfer operation, and a selection flip-flop 3 for selecting a storage element 1 and an input memory 2, which will be described later.
2. An address register 33 that holds the address supplied to the input memory 2, a 12-bit address register 35 that holds the address supplied to the memory element 1 and the memory control circuit 5 to be described later, and a 10-bit range register that indicates the amount of data to be transferred. Contains 34. address register 3
The upper two bits of 5 are selection bits that determine the transfer destination from among the four outputs F and IFO. When the upper two bits are "00", the output PIF060 is selected, and when it is "01", the output FIFO61 is selected. , when it is "10", the output FIFO
62, and when it is "11", F IF 063 is selected.

The remaining lower 10 bits are output from input memory 2 to F
It is incremented by 1 each time data is transferred to the IFO.

The range register 34 is decremented by 1 each time data is transferred from the input memory 2 to the output FIFO.

The memory control circuit 5 includes a start instruction flip-flop 31
, both signals of the selection flip-flop 32, a signal 350 of the upper two bits of the address register 35, and a read pulse and a write pulse (not shown) are input, and the memory element 1 is
, output enable signals OEI, OE2 and write enable signals W11, WE60, WE61, WE62 for input memory 2 and four output FIFOs 60 to 63.
, WE63.

Note that, depending on the logical values of each output enable signal and each write enable signal, storage element 1, input memory 2, and four outputs F IF 060 to 63 operate as shown in Table 2. That is, each memory and output FIFO is
Read operation when only the output enable signal is “o”
A write operation is performed when only the write enable signal is "0", and a high impedance state occurs when both signals are "1".

The control processor 7 controls the DMA controller 3 and
A set of start instruction flip-flops 31 and selection flip-flops 32, which are resources of the MA controller 3;
Address register 33, range register 34, and address register 35 can be read or written. In addition, a connection try request generation signal 8 is sent from the information processing device of the transfer destination.
is accepted as an interrupt. The memory element 1 is newly installed in the present invention. Its storage capacity is output FIF
The total capacity of O60 to O63 is 4 bytes, and all bits of address register 35 (1
0 bit) is supplied, and the data line is connected to the data bus 4. Figure 2 shows four output FIFOs in memory element 1.
This shows a state in which numbers 60 to 63 are assigned. Address 000-3
Output to FF FI F 060, address 400-7F
Output FIFO 61 to F, output FIFO 62 to addresses 800 to BFF, output FIFO to addresses 000 to FFF
F 063 is assigned.

Four output FIFOs 60-63 from normal input memory 2
The operation to transfer data to one of them is as follows. First, the control processor 7 uses the address register 33
The address value is set in the address register 35, and the amount of data to be transferred is set in the range register 34. At this time, the upper two bits of the address register 35 are set to ``00'' when the transfer destination is the output FIFO 60, ``01'' when the transfer destination is the output FIFO 61, and ``01'' to the output FIFO ○6.
When the output is 2, "10" is set, and when the output is F IF 063, "11" is set.

Further, all zeros are set in the remaining lower 10 bits. Subsequently, the selection flip-flop 32 is set to "0", and finally the start instruction flip-flop 31 is set to "1". When the start instruction flip-flop 31 becomes "1", DMA transfer is started.

Next, the internal configuration of the memory control circuit 5 will be explained using FIG. 3 and Table 1. FIG. 3 is a circuit diagram showing the internal configuration of memory control circuit 5 in FIG. 1. In Figure 3,
The memory control circuit 5 is composed of Nant gates 200 to 206 and a decoder 207, and receives the outputs of a start instruction flip-flop 31, a selection flip-flop 32, a signal 350 of the upper two bits of the address register 35, and a read pulse and a write pulse. is taken as input. The operation of the embodiment of the present invention including the memory control circuit 5 having such a configuration will be explained using the time charts of FIGS. 4 and 5.

Figure 4 shows normal operation, from input memory 2 to output FIF
It is a time chart when transferring data to O61. The control processor 7 sets data in the transfer source address register 33, transfer destination address register 35, and range register 34 in this order, and finally, when the start instruction flip-flop 31 is set to "1", the DMA transfer starts. will be activated.

Since the selection flip-flop 32 is originally "0", a write pulse is supplied to the write enable signal WEI of the storage element 1 by the Nant gate 200 in FIG. A read pulse is provided.

Also, since address 400 was set in the address register 35 by the control processor 7, the signal 350 is “
01" is output. The decoder 207 shown in FIG.
When the value “Ol” of the signal 350 is input, only the signal D1 is “1”.
" is output. Therefore, the write pulse is supplied only to the WE 61 by the Nant gate 204. With the above, data can be transferred from the input memory 2 to the output FI F 061, and at the same time, the same data is written to the storage element 1. In other words, the data has been backed up in the storage element 1. For each data transfer, address register 33 and address register 35 are incremented by 1, and range register 34 is incremented by 1. 1
This DMA transfer is performed until the content of the range register 34 becomes "1", and at the timing when the content of the range register 34 changes from "1" to "0", the start instruction flip-flop 31 is reset and the DMA transfer is completed. becomes.

Next, the data stored in the output FIFO 61 is then transferred to the destination information processing device. However, assume that a retry request is generated from the destination information processing device after the data transfer is completed, and is notified to the control processor 7 via the retry request generation signal 8. Then, the control processor 7 starts a retry operation, that is, an operation of transferring the data stored in the storage element 1 to the output FIFO 61.

Its operation is shown in FIG. First, the control processor 7 controls the address register 35 and the range register 3.
4, set the same address value and the same data transfer amount as those set when data was transferred from the input memory 2 to the output FIF061.

The control processor 7 then selects the selection flip-flop 32
is now set to "1", and finally the start instruction flip-flop 31 is set to "1" to start DMA transfer.

When DMA transfer is started, the start instruction flip-flop 31 is "1" and the selection flip-flop 32 is "1", so the output enable signal σ from the input memory 2 is output by the Nant gate 202 in FIG. is always supplied with "1", and the data stored in the input memory 2 is not output to the data bus 4.

On the other hand, a read pulse is supplied by the Nant gate 201 to the output enable signal OE1 of the storage element l. In addition, the write enable signal WE61 of the output FIFO61
A write pulse is supplied to , as in the case of normal transfer. As a result of the above, the data stored in the storage element 1 is outputted to the data bus 4 and transferred to the output FIFO 51. For each data transfer, the address register 35
is incremented by plus one, and range register 34 is incremented by minus one. For one DMA transfer, the contents of the range register 34 are “
1”, and the contents of the range register 34 become “1”.
At the timing when the value changes from "1" to "0", the start instruction flip-flop 31 is reset and the DMA transfer is completed.

By the above-described operation, the data that caused the retry request to be generated in the information processing device of the transfer destination can be reloaded from the storage element 1 to the output FIFO 61. and output F
The retry operation is completed by transferring the data reloaded to the IF 061 to the information processing device again.

In most of the present embodiment, the output FIF061 is described as a representative among the four output FIFOs in order to show a concrete example, but the same description can be made for the other three as well. The output FIFO is selected by the value set in the upper two bits of the address register 35 by the control processor 7.

Further, in this embodiment, the number of output FIFOs is set to four, but the number is not limited to four and can be expanded.

〔Effect of the invention〕

As explained above, the present invention has the following excellent effects.

(2) After the input memory transfers data to the output FIFO, it can immediately receive the next data from the source information processing device, resulting in improved performance.

■ When a retry occurs, data is retransferred from the storage element to the output FIFO, thereby increasing the recovery rate from intermittent failures.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention. Figure 2 shows the output F to the storage element of the data transfer device of the present invention.
A diagram showing IFO allocation. FIG. 3 is a block diagram of the memory control circuit of the data transfer device of the present invention. FIG. 4 is a time chart of normal data transfer by the data transfer device of the present invention. FIG. 5 is a time chart of data transfer during IJ) write of the data transfer device of the present invention. 1...Storage element, 2...Input memory, 3...DM
A controller, 4...Data bus, 5...Memory control circuit, 7...Control processor, 8...Retry request generation signal, 31...Flip-flop for start instruction, 32...Selection flip-flop 33...Transfer source address register, 34...Range register, 35
... Address register of transfer destination, 60-63... Output FIFO 1350... Upper 12 bits of address register of transfer destination, 351... Lower 10 bits of address register of transfer destination, WEI... Storage element write enable signal of OEJ,... output enable signal of storage element, σπ7... output enable signal of input memory, WE60... write enable signal of output FIFO 60, WE61... write enable of output F r F061 Signal, WE62...Write enable signal of output FIF062, WE63...Output FIF06
4 write enable signal, 200 to 206...Nant gate, 207...2 input 4 output decoder.

Claims (1)

[Claims] 1. An input memory that stores input data, and a plurality of output FIs that temporarily store the contents of the input memory, output it to an external device, and output the contents again based on a retry request.
FO, and access control means for controlling access to the input memory and the output FIFO, and the access control means controls the input memory and one of the plurality of output FIFOs to control the contents of the input memory. A data transfer device including a write control means for reading and writing to this one output FIFO, comprising a storage means for temporarily storing the contents of the input memory,
The access control means includes a rewrite control means that controls the storage means and the output FIFO based on the retry request, reads the corresponding contents of the storage means, and writes them into the output FIFO as contents to be output again. A data transfer device characterized by: 2. The storage means includes a storage element having a capacity greater than the total capacity of the plurality of output FIFOs, and the storage element includes areas corresponding to each of the plurality of output FIFOs.
The data transfer device described. 3. The storage means includes simultaneous write control means that controls the storage element simultaneously with the write control of the write control means to write the contents of the input memory into an area corresponding to the one output FIFO. The data transfer device according to claim 1.