JPH0454770A - Synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a pseudo synchronizing signal with simple constitution by frequency-dividing a specific number of horizontal synchronizing pulses from a synchronizing separator circuit and differentiating the specific number of horizontal synchronizing pulses subject to frequency division so as to form the pseudo vertical synchronizing signal. CONSTITUTION:A horizontal synchronizing pulse from a PLL 9 is fed to a 1/256 frequency division counter 12, in which the pulse is subject to 1/256 frequency division. An output of the counter 12 is fed to a differentiating circuit 13, where the output signal is differentiated. The output of the circuit 13 is fed to a position (b) of an input terminal of a switch circuit 10. On the other hand, when a video signal presence detection circuit 15 detects a video signal, the switch circuit 10 is thrown to the position of the (a). When the circuit 15 does not detect a video signal, the switch circuit 10 is thrown to the position of the (b). When no video signal is inputted from the circuit 10, a separated vertical synchronizing signal is outputted from a synchronizing separator circuit 8 and when no video signal is inputted, a pseudo vertical synchronizing signal generated by generated from the counter 12, the differentiating circuit 13 and a shaping circuit 14 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal generation circuit that outputs a pseudo vertical synchronization signal when there is no video signal.

[Summary of the invention]

In a synchronization signal generation circuit suitable for displaying characters, the frequency of the horizontal synchronization pulse from the synchronization separation circuit is divided by 256, and the horizontal synchronization pulse divided by 256 is differentiated to generate a pseudo vertical synchronization signal. By forming a pseudo vertical synchronizing signal and outputting this pseudo vertical synchronizing signal when there is no video signal, it is possible to obtain a pseudo vertical synchronizing signal with a simple configuration.

[Conventional technology]

BACKGROUND ART Character signals are superimposed on video signals, and various operating states such as set channels are displayed as characters on a monitor screen. When displaying characters on a monitor screen in this manner, when no video signal is input, the synchronization system enters a free-run state, causing disturbances in the displayed characters. Therefore, when displaying various operating states as characters on the monitor screen, a pseudo-image synchronization signal is generated when no video signal is input so that the displayed characters do not become distorted even when no video signal is input. It is necessary to do so.

If the synchronization signal separated from the input video signal is supplied to the PLL to form a horizontal synchronization pulse, and the oscillation frequency of this PLL in the free run state is set near the horizontal frequency (15,75kHz), the video signal can be Even when no signal is input, a pseudo-image horizontal synchronization pulse approximately equal to the horizontal frequency can be obtained. In the NTSC system, the relationship between the horizontal frequency and the field frequency is 15.75kHz/60Hz=262, so if the pseudo-image horizontal pulse output from the PLL is divided by 262, a pseudo-image vertical synchronization pulse can be obtained. can.

Problems to be Solved by the Invention E] A video component system has been proposed in which an 8mm VTR deck, a liquid crystal color monitor, and a tuner are each separated, and an AV system can be constructed by combining them. Such a video component system is provided with a character generator for displaying various operating states on the tuner. The signal from this tuner is then displayed on a liquid crystal color monitor.

In such a video component system, as mentioned above, in order to prevent display characters from being distorted even when no video signal is being input, a circuit is provided that generates a pseudo-image synchronization signal when no video signal is being input to the tuner. It is necessary to do so.

In such a small system, it is necessary to reduce the size and cost of this circuit.

Conventional circuits that divide the horizontal synchronization pulse output from the PLL by 262 to form pseudo-vertical pulses cannot be configured using binary counters, and are therefore difficult to miniaturize.
This will increase costs.

Therefore, an object of the present invention is to provide a synchronization generation circuit that can generate a pseudo synchronization signal with a simple configuration.

[Means to solve the problem]

In this invention, the horizontal synchronization pulse from the synchronization separation circuit is
This is a synchronization signal generation circuit which differentiates a horizontal synchronization pulse whose frequency is divided by 6 and frequency by 256 to form a pseudo vertical synchronization signal, and outputs the pseudo vertical synchronization signal when there is no video signal.

[Effect]

When no video signal is input, a pseudo vertical synchronization signal is formed from the horizontal synchronization pulse from the PLL 9 by the 1/256 frequency division counter 12, the differentiation circuit 13, and the shaping circuit 14.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The present invention is used, for example, in a synchronization generating circuit for a tuner in a video component system in which an 8 mm VTR deck, a liquid crystal color monitor, and a tuner are each separated and can be constructed by combining them.

FIG. 1 shows an embodiment of the present invention used in a synchronization generating circuit of such a tuner. In FIG. 1, a received signal from an antenna l is supplied to a tuner circuit 2. In FIG. Based on the channel setting signal from the controller 5, the tuner circuit 2 converts the received signal of a desired channel into a predetermined intermediate frequency signal.

The output of the tuner circuit Is2 is supplied to the video detection circuit 4 via the IF amplifier circuit 3. A video detection circuit 4 detects the video signal of the receiving channel. This detected video signal is output from an output terminal 7 via an adder circuit 6.

At the same time, the output of the video detection circuit 4 is transmitted to the sync separation circuit 8.
is supplied to The horizontal and vertical synchronizing signals are separated by the synchronization separation circuit 8. The vertical synchronizing signal separated by zero is supplied to the input terminal on the switch circuit 1oOa side. The horizontal synchronizing signal separated by zero is supplied to the PLL 9.

The PLL 9 generates a horizontal synchronization pulse synchronized with the horizontal synchronization signal based on the horizontal synchronization signal from the synchronization separation circuit 8 . 20 The oscillation frequency of the PLL 9 in a free run state is approximately a horizontal frequency.

The horizontal synchronizing pulse from the PLL 9 is supplied to the character generator 11, and the I/256 frequency division counter 1
2. 1/25f 1 lap counter 12, PL
The horizontal synchronization pulse from L9 is divided by 1/256. The output of this 1/256 frequency division counter 12 is supplied to a differentiating circuit 13.

A differentiation circuit 13 differentiates the output of the 1/256 frequency division counter 12. The output of the differentiating circuit 13 is supplied to b input terminals of the switch circuit 10 via the shaping circuit 14.

Further, the output of the video detection circuit 4 is supplied to a video signal presence/absence detection circuit 15. In the video signal presence/absence detection circuit 15,
The presence or absence of a video signal is detected.

The output of this video signal presence detection circuit 15 is supplied to the switch circuit 10 as a switch control signal.

When a video signal is detected by the video signal presence detection circuit 15, the switch circuit 10 is switched to the a side. When the video signal detection circuit 12 does not detect a video signal, the switch circuit 10 is switched to the b side.

The switch circuit 10 outputs the vertical synchronization signal separated by the synchronization separation circuit 8 when the video signal is input manually, and when the video signal is not input, the vertical synchronization signal is 1/25.
A pseudo vertical synchronization signal formed by the divide-by-6 counter 12, the differentiation circuit 13, and the shaping circuit 14 is output.

In other words, when a video signal is input, the switch circuit 10 is switched to the a side, so the sync separation circuit 8
The vertical synchronization signal separated by is outputted via the switch circuit 10.

When no video signal is input, synchronize and separate times! 8
At this time, when the synchronization signal cannot be separated, the PLL 9 is in a free run state, and a horizontal synchronization pulse having a frequency substantially close to the horizontal frequency is output.

This horizontal synchronizing pulse (FIG. 2A) is supplied to the 1/256 frequency division counter 12, and as shown in FIG. 2B, 1/25
The frequency is divided by 6. The output of the 1/256 frequency dividing counter 12 is differentiated by a differentiating circuit 13 as shown in FIG. 2C. This differentiated signal is shaped by a shaping circuit 14 to form a pseudo vertical synchronizing signal as shown in the second diagram.

The relationship between the horizontal frequency and field frequency in the NTSC system is (15,75kHz/60Hz=262), so if the horizontal synchronization pulse is divided by 262 to form a pseudo vertical synchronization signal, the horizontal direction of the screen is slightly shorter, but it can be used sufficiently to stably display characters when there is no video signal. Since this 1/256 frequency division counter 12 can be realized with 28 binary counters, the circuit size and cost can be reduced.

Note that if the oscillation frequency of the PLL 9 in the free run state is slightly lowered, it is possible to avoid shortening the screen in the horizontal direction. In other words, since the relationship between the horizontal frequency and field frequency in the NTSC system is (1/262), it becomes 256/262ζ0.977, so the oscillation frequency in free run of the PLL is reduced by about 2 to 3% to the original horizontal frequency. Setting it lower will prevent the screen from becoming shorter in the horizontal direction.

The output of the switch circuit 10 is the character generator 11
is supplied to

The controller 5 generates display control signals corresponding to various setting conditions such as channel settings.

This display control signal is supplied from the controller 5 to the character generator 11.

The character generator 11 generates a character signal based on the display control signal from the controller 5. This character signal is supplied to the power supply circuit 6. As a result, various character signals are superimposed on the video signal.

〔Effect of the invention〕

According to the present invention, when no video signal is input, a pseudo vertical synchronization signal is formed from the horizontal synchronization pulse from the PLL 9 by the 1/256 frequency division counter 12, the differentiation circuit 13, and the shaping circuit 14. 1/256 frequency division counter 12
Since it can be constructed with an 8-bit binary counter, it is easy to downsize and reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram used to explain the embodiment of the invention. Explanation of main symbols in the drawings 8: Synchronous separation circuit, 9: PLL. 10: Switch circuit, 12: 1/256 frequency division counter, 13°: Differential circuit, 15: Video signal presence/absence detection circuit.

Claims (1)

[Claims] The frequency of the horizontal synchronization pulse from the synchronization separation circuit is divided by 256, and the horizontal synchronization pulse frequency-divided by 256 is differentiated to form a pseudo vertical synchronization signal, and when there is no video signal, the pseudo vertical synchronization signal is output. synchronous signal generation circuit.