JPH04557A - Vector processor - Google Patents

Abstract

PURPOSE:To reduce overhead due to the saving of the contents of a vector register at the time of switching a process by providing the vector processor with a virtual/physical vector register number conversion table and a control table for storing vector register numbers and memory saving addresses. CONSTITUTION:The vector processor regards a vector register (VR) number specified by a vector instruction as a virtual number, and at the time of process switching, refers the conversion table and converts the virtual VR number into a physical VR number. Consequently, the VR 4 for the old process is protected and a VR 4 for a new process is secured. When a bus is still idle after starting the execution of the new process, the contents of the VR 4 of the old process are saved in a memory and the VR 4 necessary for the reexecution of the old process is restored while referring the control table. Thereby, the generation of overhead is reduced and high performance is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vector processor for an information processing device.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional vector processor. In the figure, (1) is an instruction register containing hector instructions to be executed, and (2) is a rotor register containing a hector instruction to be executed.
Load vibe for queuing data, (3) is a crossbar switch that assigns a manual path to the vector register by the vector register number (hereinafter referred to as VR number) of the instruction register (1), (4) is the vector register, (5) is the VR number of the instruction register (1) and the vector register (4
), a crossbar switch that assigns the output path from (
6) is a store pipe for queuing store data to memory, and (7) is an arithmetic unit.Next, the operation will be explained. When performing normal vector operations, when a VR number is input from the instruction register (1) to the crossbar switch (3), the data queued in the rotor pipe (2) from the memory is transferred to the crossbar switch in correspondence with the VR number. (3) and is rolled into a predetermined vector register (4) through the manual path allocated by (3). next,
The loaded data is input to the arithmetic unit (7) through output pulses assigned by the crossbar switch (5) according to the VR number, and vector calculation is performed. The calculation result is stored in a predetermined vector register by the input path allocated again by the crossbar switch (3). As described above, when a process switch occurs while data is being loaded or calculation results are stored in the vector register, all contents of the vector register (4) in use are saved to the memory save area. do.

In addition, when a process switch occurs again and the originally executed process is to be executed again, the contents of the saved vector register (4) are restored from memory. These processes are performed during the process of a process switch. (Problem to be solved by the invention) Since conventional vector processors are configured as described above, each time a process switch is performed, the vectors in use are
The contents of registers must be transferred between memories, which makes process switches take a very long time, and
There was a problem in that the execution performance of the vector processor deteriorated.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a vector processor that reduces the overhead caused by saving the contents of vector registers at the time of process switching.

[Means to solve the problem]

A vector processor according to the present invention includes a plurality of vector registers, a first crossbar switch that allocates a manual bus of rotary data from the memory to these vector registers, and stores the vector registers in the memory. A second crossbar switch that allocates a data output path, an instruction register that outputs a bus allocation instruction for each crossbar switch as a virtual vector register number, and a physical vector that manually inputs the output virtual vector register number to the crossbar switch. A conversion table for converting into register numbers and a management table for storing vector register numbers of vector data temporarily saved in memory and memory save addresses are provided.

[Effect]

The vector processor according to the present invention regards the VR number indicated by the vector instruction as a virtual one, and
It has a conversion table for converting to R numbers, and when a process switch is performed, the conversion table is referred to and the virtual VR number is replaced with the physical VR number, thereby protecting the vector register of the old process and converting it to the new process. After allocating a vector register for a process and starting execution of the new process, when the bus (data transfer path to memory) is free, save the contents of the old process's vector register to memory. , also has a management table in which the old process number, register number, and save address are written, so that when the old process is re-executed, the necessary vector registers can be restored by looking at the management table. It is.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the instruction register where the vector instruction to be executed is stored, (2) is the rotary pipe that queues the load data from memory, and (3) is the physical vector register number (hereinafter referred to as PVR number). ), a crossbar switch that assigns a human-powered bus to a vector register,
(4) is a vector register, (5) is a crossbar switch that allocates the output path from vector register (4) by PVR number, (6) is a store vibe that queues store data to memory, ( 7) is a computing unit,
(8) is a V having a table (VRT) for converting a vector register number (VR) to a PVR and a management table (SAT) for saving and restoring vector registers in memory at the time of a process switch.
This is an R number converter.

Next, the operation will be explained. VR number is 1-4, PVR
The numbers are also 1-4.

■Process 1 executes, VRI of vector register,
Suppose you use VR2. At this time, the VR conversion table (hereinafter VRT) in the converter (8) becomes as shown in FIG. 2(a).

■Assume that the process switch is turned on, process 2 is executed, and uses vector registers VRI and VR2. At this time, the VRT associates VRI, 2 with PVRs 3 and 4, respectively, and starts saving PVRI, 2 in the memory (at this time, saving = 1). In the management table (hereinafter referred to as SAT) that stores save addresses, process number = 1,
VR number = 1 or 2, save address = 1000
Or 1100 is recorded.

When the saving of the contents of PVRI, 2 is completed, the VRT at this time will be saved = 0 and saved = 1.

The SAT becomes as shown in FIG. 2(b).

■Assume that the process switch is turned on and process 3 is executed, using only the vector register VRI. At this time P
Since VR=1 has been saved, VRI is made to correspond to PVRI. PVRs 3 and 4 are saved in the memory, and when the save is completed, the VRT and SAT become as shown in FIG. 2(C).

■The process switch is turned on and process 1 is re-executed. At this time, VR = 2 of process 1 remains in the vector register as PVR = 2, so use it as is, and since VR = 1 does not remain in the vector register, save address = 1000 from SAT. Bring it back. PVRI is saved in memory. When the save is completed, the VRT and SAT will be as shown in FIG. 2(d).

In the above embodiment, both the number of VRs and the number of PVRs are set to four, but these numbers are arbitrary. The number of store pipes, load pipes, arithmetic units, etc. is arbitrary.

(Effects of the Invention) As described above, according to the present invention, a converter is provided that converts a VR number into a PVR number, and it is possible to protect and secure a VR by simply changing the correspondence between a VR number and a PVR number. Therefore, the overhead due to vector register saving at the time of vector switching is reduced, and a high-performance vector processor can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a vector processor according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the transition of conversion tables and management tables for each process switch, and FIG. 3 is a block diagram of a conventional vector processor. be. In the figure, (1) is the instruction register, (3), (5
) is a crossbar switch, (4) is a vector register, and (8) is a vector register number converter. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Memory

Claims (1)

[Claims] a plurality of vector registers; a first crossbar switch that allocates input paths for loading data from memory to these vector registers; and a second crossbar switch that allocates output paths for data to be stored in memory to each of the vector registers. a crossbar switch, an instruction register that outputs a path allocation instruction for each crossbar switch as a virtual vector register number, and a conversion table that converts the output virtual vector register number to a physical vector register number input to the crossbar switch. A vector processor comprising: a management table that stores vector register numbers of vector data temporarily saved in memory and memory save addresses;