JPH0455948A - Dummy cycle detection system for computer program tracing device - Google Patents

Abstract

PURPOSE:To accurately trace only the address bus signal of a valid bus cycle by receiving the address bus signal via a pull-up resistance and detecting a dummy cycle when all bits of the received signal are set the active levels. CONSTITUTION:The signal taken out of an address bus of a computer 2 is received via a pull-up resistance 6. Then a dummy cycle signal DC is set at a high level ('1') in a dummy cycle of a microprocessor 2. Meanwhile the address bus signal inputted to a passed address tracing device 8 is invalid and therefore inhibited to be traced by the device 8 as the passed address information. As a result, only the address bus signal of a valid bus cycle is accurately traced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dummy cycle detection method in a computer program tracing device, and more specifically, detects a dummy cycle of a computer and detects the address bus signal of the computer in the dummy cycle. This allows accurate tracing of transit addresses by excluding them.

[Conventional technology]

Performs inspection and evaluation of computer programs.

In order to correct the error, that is, to perform debugging, it is necessary to perform a program test.

A 0-pass address trace test, which has traditionally been known as a 1-pass address trace test as a program test, basically involves a computer running a program to be tested, and sequentially capturing address information during execution. It consists of recording (tracing). As a method for recording address information actually executed sequentially, that is, passing address information, addresses in the trace memory are made to correspond to program addresses, and data indicating passing (for example, bit gr 1 '') is performed (see Patent No. 1134367).

By simply tracing passing addresses, it is not possible to determine whether a branch is taken or not taken at a branch point in a program. Therefore, in Japanese Patent Application No. 59-199367 (Japanese Unexamined Patent Publication No. 61-77943) related to the application filed by the present applicant, it is determined based on the continuity of passed addresses whether 5 branches are taken or not. It is disclosed that trace data regarding a branch taken and trace data regarding a branch not taken are respectively created and stored separately according to the determination result.

Also, in order to evaluate the trace data, the coverage (
It is also practiced to calculate the coverage rate) and use the calculated coverage as a measure (point S) that specifically indicates the test result.

[Problem to be solved by the invention]

By the way, the bus cycle state in the computer under test includes actual memory address access and I1.
There are valid bus cycles that access the 0 area and dummy cycles that are not actually accessed.

If a dummy cycle appears cyclically between valid bus cycles, it is necessary to accurately detect it and exclude it from the passing address trace. This is because if the address bus signal during the dummy cycle is traced in the same manner as the address bus signal during the valid bus cycle, the following problem will occur.

a) Since the continuity of passed addresses cannot be determined, it becomes difficult to determine whether a branch is taken or not taken as described above.

b) Even if the same address information persists, it is divided by dummy cycles,
This is uneconomical because it becomes impossible to compress and record the same address information that persists.

C) If address bus signals during dummy cycles are also traced, the trace memory will be wasted and the space for recording address bus signals during valid bus cycles will be reduced.

These inconveniences can be solved relatively easily if the bus cycle identification signal is output from the computer side, since the tracing device only needs to detect the dummy cycle based on this bus cycle identification signal. .

However, in the case of a type of computer that does not output a bus cycle identification signal, the above problem cannot be solved.

The present invention has been made in view of the above points, and solves the various problems mentioned above by making it possible to easily detect dummy cycles even when applied to a type of computer that does not output a bus cycle identification signal. It is an object of the present invention to provide a dummy cycle detection method in a computer program tracing device that can solve the problem.

[Means to solve the problem]

The dummy cycle inspection method according to the present invention includes a receiving circuit that receives a signal taken out from an address bus of a computer via a pull-up resistor, and outputting a dummy cycle signal when the output of the receiving circuit is at an active level for all bits.
The apparatus further includes a dummy cycle detection circuit that prohibits tracing of a signal appearing on the address bus in response to the dummy cycle signal as passing address information of the computer.

[For production]

The signal level state of the address bus of a computer is three states, and in a valid bus cycle, it takes a high level (“1”) or low level (1'o) state depending on the value of the address signal, but in a dummy cycle, it takes a high level (“1”) or a low level (1'o) state. Therefore, in the present invention, a signal taken out from the address bus of the computer is received via a pull-up resistor.

Then, when the address bus is in a floating state, it is received by the pull-up resistor as a high level signal and an active level signal. Since all bits of the address bus are in a floating state in the dummy cycle, the pull-up to the active level causes the output of the receiving circuit to have all bits at the active level. As a result, the dummy cycle can be inspected when the output of the receiving circuit is at all bits active level, and a dummy cycle signal is output at that time. By using this dummy cycle signal, the above-mentioned problems a'' and c can be solved by prohibiting the signal appearing on the address bus from being traced as passing address information of the computer.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, a device to be measured 1 is controlled by a computer, and a microprocessor 2, for example, is used as the computer. The program tracer 3 sequentially inputs the address information of the program being executed in the microprocessor 2 from the address bus of the microprocessor 2 via the address bus cable 4.

Performs necessary computer program tracing processing. In this case, the signal state of the address bus of the microprocessor 2 is directly applied to the program tracer 3 via the address bus cable 4.

Therefore, the address bus signal state in the dummy cycle of the microprocessor 2 is also applied to the program tracer 3 via the address bus cable 4. In the address bus signal state in the 6 dummy cycles, all bits are in a floating state, that is, at a tri-state level. On the other hand, in a valid bus cycle, each bit becomes high level ("1") according to the value of the address signal.
Or it becomes a low level ('0'') state.

On the program tracer 3 side, a reception circuit 5 receives the signal from the address bus cable 4 .

The receiving circuit 5 includes a pull-up resistor 6 and a receiving amplifier element 7 for each bit. By providing the pull-up resistor 6, if the signal level of the address bus cable 4 is high level (1") or low level (0"), it will remain at high level (1") or low level ("0").
”) is given to the corresponding receiving amplifier element 7, but if the signal level of the address bus cable 4 is in a floating state, that is, a tri-state level bit, a high level (“1”) bit signal corresponds to it. The signal is applied to the receiving amplifier element 7.

The output of the receiving circuit 5 is input to a passing address trace group 8 and a dummy cycle detection circuit 9.

In the passing address trace group FL8, the signal given from the receiving circuit 5 is sequentially taken in as address information being executed by the microprocessor under test 2, and this is recorded (traced). For example, this passing address tracing device 8
, which creates and stores trace data regarding branch establishment or branch failure according to addresses passed through the program, has an address continuity determination unit 81 and read/write memories 82 and 83. The address continuity determination unit 81 determines the continuity of the passing address information provided from the receiving circuit 5, and determines that the branch is not taken when the address is continuous, and that the branch is taken when it is discontinuous. The memory 82 stores trace data regarding branch establishment.
1” is written at the address where it is determined that the address corresponds to the program address and 1 branch is established,
The memory 83 stores trace data related to branch failure, and the address corresponds to the program address, and 11 is written at the address where it is determined that the branch is not taken.
” and writes RO17 at other addresses. This passing address tracing device 8
Not limited to the above.

Other configurations may also be used.

In the dummy cycle detection circuit 9, the output of the receiving circuit 5 is at all bits active level, that is, in this example, high level (111
”), a dummy cycle signal DC is output, this dummy cycle signal DC is given to the passing address trace group [8, and the signal appearing on the address bus corresponding to the dummy cycle signal DC is used as passing address information of the computer. Tracing is prohibited.An example of the dummy cycle detection circuit 9 is, as shown in FIG. Level (“1”)
When the dummy cycle signal DC is high level (1”
) outputs a signal.

As mentioned above, in the address bus signal state during the dummy cycle of the microprocessor 2, all bits are in a floating state, that is, at a tri-state level. (1") signal is input, and the signal given to the dummy cycle detection circuit 9 as its output becomes high level ("1") for all bits. Therefore, during the dummy cycle of the microprocessor 2, the dummy cycle signal DC is high. level (“1”), and correspondingly, the address bus signal input to the transit address trace group [8 is invalid, so it is prohibited to trace this as transit address information in the transit address trace device 8. be done.

Note that when all bits of the address signal are at high level (1") in a valid bus cycle, the dummy cycle signal DC is output even though it is not a dummy cycle, but this is almost never the case. There are some processors that use all "1" addresses as vector addresses, but
In that case, it is possible to determine that it is a vector address from the signal state of the address bus around 1.

This problem can be dealt with by configuring the dummy cycle detection circuit 9 in this way.

Note that although the active level has been described above as a high level ("l"), the active level may be a low level (0") conversely.

Further, the address bus signal applied to the passing address trace device 8 may not be pulled up by the pull-up resistor 6.

〔Effect of the invention〕

As described above, according to the present invention, an address bus signal is received via a pull-up resistor, and a dummy cycle is detected when all bits of the received signal are at active level. By excluding the address bus signal at the time of , it becomes possible to accurately trace only the address bus signal of the valid bus cycle. It has this excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the dummy cycle detection circuit in FIG. 1. 1... Device under test, 2... Microprocessor, 3
...Program tracer, 4...Address bus cable, 5...Receiving circuit, 6...Pull-up resistor, 7
. . . Reception amplifier element, 8 . . . Passing address tracing device, 9 . . . Dummy cycle detection circuit.

Claims (1)

[Scope of Claims] A computer program tracing device that sequentially inputs address information of a program being executed in a computer and traces the addresses passed by the program, comprising: a signal taken out from an address bus of the computer via a pull-up resistor; a receiving circuit for receiving data; and a dummy cycle signal is output when all bits of the output of the receiving circuit are at an active level, and a signal appearing on the address bus corresponding to the dummy cycle signal is traced as passing address information of the computer. A dummy cycle detection method in a computer program tracing device, comprising a dummy cycle detection circuit that prohibits dummy cycle detection.