JPH0456253A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0456253A JPH0456253A JP2168008A JP16800890A JPH0456253A JP H0456253 A JPH0456253 A JP H0456253A JP 2168008 A JP2168008 A JP 2168008A JP 16800890 A JP16800890 A JP 16800890A JP H0456253 A JPH0456253 A JP H0456253A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- stress
- chip
- hybrid
- center
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、突起電極を有する半導体集積回路における
突起電極の配置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the arrangement of protruding electrodes in a semiconductor integrated circuit having protruding electrodes.
近年、電子回路の高密度実装技術の進展はめざましく・
特に半導体応用製品の高機能化の中心&ゴモノリシンク
IOの大規模化及びマルチチン71iJ装指向に向って
いる。これらの高密度実装に応える一手段として半田突
起電極を有するフリップチップ10が採用されてきてい
る。In recent years, there has been remarkable progress in high-density packaging technology for electronic circuits.
In particular, the focus is on increasing the functionality of semiconductor application products, increasing the scale of Gomonori Sync IO, and oriented towards multi-chin 71iJ equipment. A flip chip 10 having solder protrusion electrodes has been adopted as a means to meet these high-density packaging requirements.
IOの実装としてフリップチップIOを用いたフェース
ダウンボンディングを採用する目的は、第1に高密度実
装、第2に組立プロセスの簡便化、第8に接続部の機械
的強度の向上等があげられる。The purposes of adopting face-down bonding using flip-chip IO for IO mounting are: firstly, high-density mounting, secondly, simplifying the assembly process, and eighthly, improving the mechanical strength of the connection part. .
特に自動車用の/、−1イブリツドIO等では高信頼性
の要求から接続部の強度向上が重要視される。In particular, in /, -1 hybrid IO for automobiles, etc., it is important to improve the strength of the connection part due to the requirement for high reliability.
第2図は従来採用されているフリップチップの電極配置
及びその実装例を示すものである。FIG. 2 shows the electrode arrangement of a conventional flip chip and an example of its mounting.
同図イは7リンプチツプの突起電極(以下バンプと称す
る)の配置を示しており、1はフリップチップIC.2
はバンプであり、従来、10のパターン設計上最もパタ
ーン効率が良いチップの最外周に沿って複数のバンブを
配置していた0同図口は、イ図で示したフリップチップ
IOIを実装したへイブリントIOの断面図であり、フ
リップチップIOIは導体配線が施されたセラミック基
板3上に半田付けされ、更にセラミック基板3は放熱の
ためヒートシンク4上に接着樹脂5を介して接着されて
いる。6はケースである。そしてこのハイブリッドIO
は最終的にユーザーのセントに組み付けられる際、ネジ
7によって締め付けられるが、このときヒートシンク4
の平面度や反りの状態によって、ハ図に示すネジ締め方
向(矢印)の応力がハイブリッド10内部に加わること
があるO
〔発明が解決しようとする課題〕
従来の7リツプチツプIOを実装したハイブリッドエ0
は以上のように構成されているため、ネジ締めによる応
力方向が実装されたフリップチップIOの対角線方向と
一致した場合、その応力線上付近にあるチップのコーナ
ーバンプの半田付は部分に応力が集中し、実使用におい
て断線に到るという欠点があった。Figure A shows the arrangement of protruding electrodes (hereinafter referred to as bumps) of a 7 limp chip, and 1 shows the arrangement of protruding electrodes (hereinafter referred to as bumps) of a flip chip IC. 2
are bumps, and conventionally, multiple bumps were placed along the outermost periphery of the chip, which had the highest pattern efficiency in terms of pattern design. 1 is a cross-sectional view of an iblint IO, in which a flip-chip IOI is soldered onto a ceramic substrate 3 provided with conductor wiring, and the ceramic substrate 3 is further bonded onto a heat sink 4 via an adhesive resin 5 for heat dissipation. 6 is a case. And this hybrid IO
When it is finally assembled to the user's center, it is tightened with the screw 7, but at this time the heat sink 4
Depending on the flatness and warpage of the hybrid 10, stress in the screw tightening direction (arrow) shown in Figure C may be applied to the inside of the hybrid 10. 0
is configured as described above, so if the stress direction due to screw tightening matches the diagonal direction of the mounted flip chip IO, stress will be concentrated in the soldered part of the corner bump of the chip near the stress line. However, there was a drawback that wire breakage occurred in actual use.
この発明は以上のような従来の問題京を解決するために
なされたもので、フリップチップのコーナーのバンブ半
田付は部に集中する応力を他のバンプに分散し、特定方
向の応力に対する従来品の弱点を解消し・信頼性の高い
ハイブリッドIOを提供するものである。This invention was made to solve the conventional problems as described above. Bump soldering at the corner of a flip chip disperses the stress concentrated in one part to other bumps, and the conventional product handles stress in a specific direction. This solution solves the weaknesses of the system and provides highly reliable hybrid IO.
この発明に係る半導体集積回路装置は、ICチップ内に
設けられた突起電極の配置をあらゆる方向に対する応力
集中を軽減するためにICチップの中央部に、電気的な
機能を持たない、基板との機械的接続のみを目的とした
バンプを配置したものである。In the semiconductor integrated circuit device according to the present invention, in order to reduce the stress concentration in all directions, the protruding electrodes provided in the IC chip are arranged in the central part of the IC chip with a substrate having no electrical function. Bumps are placed for the sole purpose of mechanical connection.
この発明における半導体集積回路装置は、4角形の外周
に沿って配置されたバンプを有するICチップの中央部
に、電気的な機能を持たないバンプを設けることで、セ
ント組み付は時に受けるICCランプンブ半田付は邪へ
の応力集中に対し、応力線上にあるバンプとバンプの距
離が短かくなり、バンプへの応力集中が軽減される。In the semiconductor integrated circuit device of the present invention, a bump having no electrical function is provided in the center of an IC chip having bumps arranged along the outer periphery of a rectangle. Soldering causes stress concentration on the bumps, but the distance between bumps on the stress line becomes shorter, reducing stress concentration on the bumps.
以下・この発明の一実施例)!i−図について説明する
。第1図において、2aはIOチンプlの中央部に配置
された、電気的な機能を持たないバンプである0なお、
その他の構成は上記第2図にボしたものと同様であるの
で、説明を省略する0以上のような構成下で本発明によ
るバンプ配置を有するフリップチップICを実装した場
合、ヒートシンクのネジ締め方向からの応力がバンプ半
田付は部に加わっても、応力線上に位置するバンプとバ
ンプの距離が従来に比べ約にに短かくなっているため、
各バンプが受ける応力は軽減されることになる。The following is an example of this invention)! The i-diagram will be explained. In FIG. 1, 2a is a bump that has no electrical function and is placed in the center of the IO chimp l.
The other configurations are the same as those shown in FIG. Even if stress is applied to the bump soldering part, the distance between the bumps located on the stress line is approximately shorter than before.
The stress experienced by each bump will be reduced.
以上のようにこの発明によれば、フリップチップIOの
中央部に、電気的な機能を持たないバンプを追加するこ
とで、あらゆる方向からの外部応力に対し、各バンプが
受ける応力を軽減することが可能となり・信頼性の高い
ハイブリッドIOを提供し得る効果がある。As described above, according to the present invention, by adding a bump that does not have an electrical function to the center of the flip chip IO, it is possible to reduce the stress that each bump receives from external stress from all directions. This has the effect of making it possible to provide highly reliable hybrid IO.
第1図はこの発明の一実施例を示すもので、フリップチ
ップIOのバンプ配II1図、第2菌は従来例を示すも
のでイは第1図に対応する図、口はフリップチップIO
を実装したハイプリントIOの断面図、ハはネジ締めの
際の作用説明図である。
図中、1は7リツプチツプlO12,2&ハバンブ、3
はセラミックII、板、4はヒートシンク、5は接i樹
脂、6はケース、7はネジである。
なお図中同一符号は同一または相当部分を示す。Fig. 1 shows an embodiment of the present invention, and the bump arrangement II of the flip chip IO is shown in Fig. 1, the second bacterium shows a conventional example, and A corresponds to Fig. 1.
A cross-sectional view of the HiPrint IO mounted with the above, and C is an explanatory diagram of the action when tightening the screws. In the figure, 1 is 7 lip chips lO12, 2 & Habanbu, 3
4 is a ceramic II plate, 4 is a heat sink, 5 is a contact resin, 6 is a case, and 7 is a screw. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
するICチップの中央部に、電気的な機能を持たない突
起電極を配置したことを特徴とする半導体集積回路装置
。A semiconductor integrated circuit device characterized in that a protruding electrode having no electrical function is arranged in the center of an IC chip having a plurality of protruding electrodes arranged along the outer periphery of a rectangle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168008A JPH0456253A (en) | 1990-06-25 | 1990-06-25 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168008A JPH0456253A (en) | 1990-06-25 | 1990-06-25 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0456253A true JPH0456253A (en) | 1992-02-24 |
Family
ID=15860095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2168008A Pending JPH0456253A (en) | 1990-06-25 | 1990-06-25 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0456253A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008175400A (en) * | 2008-04-11 | 2008-07-31 | Nsk Ltd | Toroidal continuously variable transmission |
-
1990
- 1990-06-25 JP JP2168008A patent/JPH0456253A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008175400A (en) * | 2008-04-11 | 2008-07-31 | Nsk Ltd | Toroidal continuously variable transmission |
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