JPH0456331A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to reduce an occupancy area per device by constituting one party of source drain regions with an impurity diffusion layer common to each device installed to the rear side of a semiconductor substrate and forming the other party of source drain regions in a device region. CONSTITUTION:A gate control type junction transistor comprises a source region 1 common to each device installed to the rear side of a semiconductor substrate, a drain region 2 and a gate electrode 3 installed to the surface of the substrate. Therefore, compared with the structure of transistor which comprises a gate electrode formed by clamping two source/drain regions on a device region, the occupancy area for a single device 1 is reduced substantially by 50%. More specifically, the area for a transfer/transistor is virtually halved. Therefore, the transistor structure is adopted for a logical device which constitutes a logical circuit, it will be possible to reduce the occupancy area for a single device.

Description

[Detailed Description of the Invention] [Summary] Regarding semiconductor devices, particularly logic elements constituting logic circuits,
The purpose of the present invention is to provide a logic element structure that can reduce the area occupied by each element compared to the conventional one, and includes: - an element isolation insulating film selectively formed on the first main surface of a conductive type semiconductor substrate; , a gate electrode formed on the first main surface, and a first source/drain region of opposite conductivity type formed in the semiconductor substrate on the first main surface adjacent to the gate electrode;
a second source/drain region of an opposite conductivity type formed on a second main surface opposite to the first main surface of the semiconductor substrate;
a load resistance layer electrically connected to the first source/drain region; a first electrode/wiring layer electrically connected to the load resistance layer; and a first electrode/wiring layer electrically connected to the first source/drain region. A state in which a first power supply voltage is connected to the first electrode/wiring layer, and a second power supply voltage is connected to the second source/drain region. in,
The structure is such that an input signal is input to the gate electrode and an output signal is taken out from the second electrode wiring layer.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a logic element forming a logic circuit.

With the recent demand for higher integration of ICs, miniaturization of semiconductor elements is required. Therefore, it is necessary to reduce the area per element of semiconductor integrated circuits, especially the logic elements constituting logic circuits.

[Conventional technology]

MOS (M
etal Oxide Sem1conducto
Figure 7(a) shows a schematic diagram of a transistor having the structure r).
Shown below. In the figure, 1 is a source, 2 is a drain, and 3 is a gate. In this way, the conventional MOS transistor has a three-terminal structure, and carriers flowing from the source 1 to the drain 2 are controlled using the potentials of the gate 3 and the substrate.

FIG. 7(b) is an equivalent circuit of FIG. 7(a). Components that are the same as those shown in FIG. 7(a) are designated by the same numbers.

The MO3 type IC currently used is the MOS! shown above.
-Made by combining transistors.

As an example, a NOT (inverter) circuit, which is the simplest logic element, is shown in FIG. FIG. 8(a) is called a load resistance type inverter. ■8. ．． is the input voltage, ■.

, t represents the output voltage, VDD represents the power supply voltage, and R represents the load resistance. High on Vifi (hereinafter referred to as H)
, for example, when 5■ is applied, ■. u'L is OV (=L
ow, hereafter written as ri) becomes ■yo,, L (=OV)
When V is applied. uL becomes 5■.

Next, this cross-sectional view is shown in FIG. 8(b). (a) As you can see from the figure, source region 1 is ground (GN)
D), and the drain region 2 is connected to a load resistance layer 9 made of polysilicon. The load resistance layer 9 is represented by R in FIG. .

Is receiving. Also, during the manufacturing process, the drain region 2
A window is selectively opened in the first glabellar insulating film 8 (not shown), and a second electrode/wiring layer (not shown) connected to the drain region 2 through the window allows the output voltage ■ . ,
Detect. By adopting such a configuration, V ou which is inverted with respect to the input voltage Vi from the gate electrode 3
It was outputting t. Conventionally, such a N07 circuit was operated to constitute a logic element of a logic circuit.

[Problem to be solved by the invention]

However, conventional MOS (MOS) transistors are planar, meaning that the source, gate, and drain are arranged horizontally, so each element occupies a large area. Even when used in logic elements, there was a limit to the reduction of the element area.

In view of the above points, it is an object of the present invention to provide a logic element structure in which the area occupied by each element can be reduced compared to the conventional one.

[Means to solve the problem]

The present invention manufactures a semiconductor device using a gate-controlled junction transistor as a logic element constituting a logic circuit. That is, an element isolation insulating film selectively formed on a first main surface of a - conductivity type semiconductor substrate, a gate electrode formed on the first main surface, and a gate electrode adjacent to the gate electrode. A first source/drain region of opposite conductivity type formed in the semiconductor substrate on a first main surface, and an opposite conductivity type first source/drain region formed on a second main surface opposite to the first main surface of the semiconductor substrate. a conductive type second source/drain region, a load resistance layer electrically connected to the first source/drain region, and a first electrode/wiring layer electrically connected to the load resistance layer; a second electrode/wiring layer electrically connected to the first source/drain region; a first power supply voltage is connected to the first electrode/wiring layer; The configuration is such that, with the second power supply voltage connected to the drain region, an input signal is input to the gate electrode, and an output signal is taken out from the second electrode wiring layer.

If used as a child, the area occupied by each logic element can be reduced.

(Function) In the gate-controlled junction transistor structure of the present invention, one source/drain region is constituted by an impurity diffusion layer common to each element provided on the back surface of the semiconductor substrate, and the other source/drain region is constituted by an element region. Figure 3 is a schematic diagram of a gate-controlled junction transistor used in the present invention.As can be seen from the figure, the gate-controlled junction transistor has a common source for each element provided on the back surface of the semiconductor substrate. It is composed of a region 1, a drain region 2 provided on the surface of the substrate, and a gate electrode 3. Therefore, in the conventional transistor structure, which consists of two source/drain regions on the element region and a gate electrode formed to sandwich them. In comparison, the area occupied by each element is about half.In other words, the area of the transfer transistor is about half.The gate of the present invention uses such a transistor structure as a logic element constituting a logic circuit. NOT using controlled junction transistor
An example of a method for manufacturing an (inverter) circuit is shown in FIG.

See Figure 1(a).

First, a semiconductor substrate, such as silicon (Si), is prepared in advance.
Impurities are introduced into the back surface of the substrate 4 to form a source region 1 common to each element. Next, L is placed on the surface of the silicon substrate 4.
OGO3(LOCal Oxidation o
The field insulating film 5 is
form.

See Figure 1(b).

Next, about 200 thermal oxide films 6 are formed on the exposed Si substrate 4 in the element region using a conventional method.

See Figure 1(C).

Subsequently, a gate electrode 3 made of polysilicon to serve as an input electrode is formed at a predetermined position to a thickness of, for example, about 2000 using a conventional method. By forming the gate electrode 3 so as to cover the field insulating film 5 in this manner, the device area can be made wider.

From another perspective, the element area can be reduced accordingly.

See Figure 1(d).

Drain region 2 is formed by implanting impurity ions 10 using gate electrode 3 as a mask. Here, for example, arsenic ions (As") are accelerated at a voltage of 70 keV and DO3E.
Type in the amount 4E15.

See Figure 1(e).

After forming a first interlayer insulating film 8 made of PSG, for example, to a thickness of about 0.5 μm on this surface, the first interlayer insulating film 8 is formed so that a contact hole is formed above the drain region 2, as shown in the figure. 8 to RIE (Reactive
It is removed by etching using a method such as ion etching. Subsequently, the thermal oxide film 6 is also removed by etching to expose the drain region 2.

See Figure 1(f).

Next, a load resistance layer 9 made of polysilicon is formed by a conventional method so as to cover the contact hole on the drain region 2. Then, impurity ions 10 such as phosphorus ions (P') and arsenic ions (As") are implanted into this load resistance layer 9. At this time, the ion implantation conditions vary depending on how much the load resistance is set. All you have to do is choose the conditions.

See Figure 1(g).

Next, a second glabellar insulating film 11 made of, for example, PSG is formed on this surface to a thickness of, for example, about 0.5 μm. after that,
As shown in the figure, the second glabellar insulating film 11 is etched away using RIE or the like so that a contact hole is formed on the load resistance layer 9, and the load resistance layer 9 is exposed. Here, for example, the diameter of the contact hole is approximately 0.5 μm.

See Figure 1(h).

Finally, a first
The electrode/wiring layer 12 is formed to have a thickness of, for example, about 1.0 μm, as shown in the figure, and then the load resistance layer 9 and the first electrode/wiring layer 1 are formed.
Make the electrical connection of 2. Here, the first electrode/wiring layer 12
Alternatively, about 2000 polysilicon may be formed instead of aluminum. Then, impurity ions 10 are implanted into this first electrode/wiring layer to lower the resistance of the first electrode/wiring layer 12. Here, for example, phosphorus ions (P''') are accelerated at a voltage of 20 keV and a DO3E amount IE
Do it at 12. After ion implantation, heat treatment is performed to form the first electrode.
Impurities are diffused into the wiring 112.

Here, for example, annealing is performed at 900° C. for 10 minutes. Then, a protective film or the like (not shown) is formed on the first electrode/wiring layer 12 to complete the gate-controlled junction transistor of the present invention.

FIG. 2 is a cross-sectional view and a plan view of an N07 circuit using the gate-controlled junction transistor of the present invention.

The sectional view of FIG. 2(b) is exactly the same as FIG. 1(h), and shows the completed state of the logic element of this embodiment. FIG. 2(a) is a plan view of this, and FIG. 2(b) is a cross-sectional view taken along the dashed-two dotted line A-A. (a) X in the figure is (b
) As can be seen from the figure, the contact portion between the drain region 2 and the load resistor layer 9, and Y in the figure is the contact portion between the first electrode/wiring layer 12 and the load resistor N9. and,
In the figure, Z indicates that a window is selectively opened in the first glabella insulating film 8 on the drain region 2 during the manufacturing process, and a contact between the second electrode/wiring layer 7 and the drain region 2 is made through the window. represents the department.

Next, the operation of the gate-controlled junction transistor described above as a logic element will be explained with reference to FIG. FIG. 4 is a schematic diagram and a circuit diagram of an NOT (inverter) circuit using the gate-controlled junction transistor of the present invention.

The first power supply voltage v0 is supplied from the first electrode/wiring layer 12 shown in FIG. 2(b). Further, input voltages (1) and (A) are applied from the gate electrode 3 shown in FIG. 2(b).

R corresponds to the load resistance layer 9 in FIG. 2(b).

However, the R part does not have to be a resistor, but can be replaced as long as it becomes a load. Then, the back surface of the substrate becomes a common source region for each element and a second power supply voltage (2) is applied. is connected to. Also ■. ut
is formed by selectively opening a window (not shown) in the first glabella insulating film 8 of FIG. 2(b) during the manufacturing process and connecting it to the drain region 2 through the window. It is taken out from the second electrode/wiring layer (not shown). VD here
D and Vllll can be set in various ways. For example, v
What is necessary is to ground Ilm and apply a desired positive voltage to VDD. With this configuration, when ■ and A are applied to the gate electrode, ■ is inverted. , is the second electrode
It is taken out from the wiring layer 7. For example, P channel MO
In the case of an S transistor, the input electrode or gate electrode 3
When a negative voltage is applied to the gate electrode 3, the transistor is turned on, and when a zero or positive voltage is applied to the gate electrode 3, the transistor is turned off.

Further, in the case of an N-channel MOS transistor, if a positive voltage is applied to the input electrode, that is, the gate electrode, the transistor is turned ON, and if 0 or negative voltage is applied to the gate electrode, the transistor is turned OFF. If you do this, V in
is L (=Low, OV), V Out is H (=H
(high), and when vl, , is H, V out becomes low. In this way, the gate-controlled junction transistor can be applied to a logic circuit (in this case, the N07 circuit).

Next, the operating characteristics of this device will be explained. For example, in an N-type semiconductor substrate, the first power supply voltage VDD is multiplied by 5■, and the second power supply voltage V! l! FIG. 5 shows current-voltage characteristics when the input electrode 3 is grounded and a negative voltage is applied to the input electrode, that is, the gate electrode 3. Here, the input voltage is the gate voltage ■. It is expressed as the absolute value. When the voltage vG applied to the gate electrode 3 is increased in absolute value, a current I flows through the drain region 2.

becomes larger. At this time, the current ID flowing is a current flowing due to the tunnel effect between bands at the interface between the drain region and the semiconductor substrate. The magnitude of this current value depends on the gate voltage (2) and the concentration of the substrate. If you want to increase the drain current, you can increase the concentration of the substrate. Here, the gate voltage ■. If it is made too large in absolute value, junction breakdown will occur as shown in FIG. 5, so it is necessary to control the gate voltage vG within a range in which this junction breakdown does not occur.

Note that the N07 circuit described above can be used in various combinations for other logic circuits, such as an OR circuit, an AND circuit, a NOR circuit, and a NANDAND circuit. For example, FIG. 6 shows a two-man NOR circuit constructed using two N07 circuits described above. FIG. 6(a) shows a two-man powered NOR circuit, and FIG. 6(b) shows a sectional view corresponding to FIG. 6(a). A first input voltage 71 is applied from the first gate electrode 7', and the second input voltage 71 is applied to the second gate electrode 7'.
”, the second input voltage 8.2 is applied.

Then, from the first electrode/wiring layer 12 to the common load resistance layer 9
to the first power supply voltage■. is supplied. Further, from the common source region 1, a second power supply voltage vIl! l is supplied. The common load resistance layer 9 is connected to the common drain region 2 . Also, during the manufacturing process, a window is selectively opened in the first glabellar insulating film 8 (not shown), and a second electrode/wiring layer (not shown) is connected to the drain region 2 through the window. The output voltage ■ from this second electrode/wiring layer. . , to detect. If such a configuration is adopted, the first input voltage ■
8. ．． Two-man power N consisting of l and second input voltage V, ゎ2
The OR circuit is completed. Of course, the output voltage ■. .

If we further add the N07 circuit to this, we can create an OR circuit.

By combining the N07 circuit in this way, the logic elements of other logic circuits can be reduced in size.

〔Effect of the invention〕

As described above, according to the present invention, the area occupied by each element can be reduced, which greatly contributes to higher integration of ICs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the main steps for explaining one embodiment of the present invention, FIG. 2 is a cross-sectional view and a plan view of an N07 circuit using the gate-controlled junction transistor of the present invention, and FIG. FIG. 4 is a schematic diagram of the gate-controlled junction transistor of the invention; FIG. 4 is a schematic diagram and circuit diagram of the N07 circuit using the gate-controlled junction transistor; FIG. 5 is a graph showing the current-voltage characteristics of the logic element of the invention; 6 is a circuit diagram and a cross-sectional view of a NOR circuit using the gate-controlled junction transistor of the present invention,
Fig. 7 is a schematic diagram and equivalent circuit diagram for explaining a transistor having a conventional MO3 structure, and Fig. 8 is a conventional MO3 structure transistor.
FIG. 2 is a circuit diagram and a cross-sectional view of an N07 circuit using an S transistor. In the figure: Source region Drain region Gate electrode Silicon substrate Field insulating film Thermal oxide film Second electrode/wiring layer First gate electrode Second gate electrode First glabellar insulating film Load resistance layer Impurity ions Second glabellar insulation Membrane 12: First electrode/wiring layer 13: GND line ": 1': +, l, wo==:' zu, '7" 4- Schematic diagram of gated cape-type goggle transistor Figure 3 Book r Figure 6 in Vo, a circuit diagram of the mouth of a NOR using a gate boat folding type Ill type orange-combined transistor and a n-side view. BB Figure 4 Takaaki Moto's logic system's electric current, earth, bamboo, and exciting Futsufuko gate Figure 7 No. 1 (Love 1)

Claims (1)

[Claims] an element isolation insulating film selectively formed on a first main surface of a semiconductor substrate of one conductivity type; a gate electrode formed on the first main surface; A first source of opposite conductivity type formed in the semiconductor substrate on the main surface of
a drain region, and a second source region of opposite conductivity type formed on a second main surface opposite to the first main surface of the semiconductor substrate.
a drain region, a load resistance layer electrically connected to the first source/drain region, a first electrode/wiring layer electrically connected to the load resistance layer, and the first source/drain region. A first power supply voltage is connected to the first electrode and wiring layer, and a second power supply voltage is connected to the second source/drain region. A semiconductor device characterized in that an input signal is input to the gate electrode and an output signal is taken out from the second electrode wiring layer while the gate electrode is connected to the gate electrode.