JPS6185854A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6185854A JPS6185854A JP59207467A JP20746784A JPS6185854A JP S6185854 A JPS6185854 A JP S6185854A JP 59207467 A JP59207467 A JP 59207467A JP 20746784 A JP20746784 A JP 20746784A JP S6185854 A JPS6185854 A JP S6185854A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistance layer
- voltage
- diffused
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/40—Resistors
- H10D1/43—Resistors having PN junctions
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
−〔産業上の利用分野〕
本発明は、半導体装置に関し、特に同一基板上に相異な
る導電形の部分を設け、そこに相補的な特性を持つＭＯ
ＳＦＥＴを作シつけた相補形ＭＯ８集積回路（０ＭＯ８
ＩＣ）に設けられた拡散高抵抗層に関する。Detailed Description of the Invention - [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which portions of different conductivity types are provided on the same substrate, and MOs having complementary characteristics are provided thereon.
Complementary MO8 integrated circuit with SFET (0MO8
The present invention relates to a diffused high resistance layer provided in an IC).
０ＭＯ８ＩＣは、元来の低消費電力動作の利点に加えて
、高速動作が可能で、大規模集積化および素子微細化に
適する半導体装置として注目されている。In addition to its inherent advantage of low power consumption, the 0MO8IC is capable of high-speed operation and is attracting attention as a semiconductor device suitable for large-scale integration and element miniaturization.
近年、ＰＩＦ等を直接駆動できるような高耐圧トランジ
スタ、高抵抗層分有する１チツプＣΔｌ０８ＩＣの要求
が活発である。In recent years, there has been an active demand for high-voltage transistors that can directly drive PIFs, etc., and single-chip CΔ108 ICs that have high resistance layers.
第３図にＦＩＰ駆動用の出力部の例を示すが、ＦＩＰｔ
−ＩＩ動するのに、プルダウン抵抗２は数１００にΩ程
度、ｖｋｋは一数１０Ｖ程度必侠である。Figure 3 shows an example of an output section for FIP drive.
-II movement, the pull-down resistor 2 must be on the order of several hundred ohms, and vkk must be on the order of several tens of volts.
このようなプルダウン抵抗のような、高抵抗層を、同一
８ｉ基板上に形成する場合、従来は、第４図に示すよう
に、例え＃−１’Ｎ形８ｉ基板１１上に薄いＳ：０！膜
１２を成長させ、レジスト膜１３等によシマスキングし
て、例えばボロンをイオン注入することＫより、Ｐ膨拡
散層１４を形成してこれた抵抗としていた。しかるＫこ
のような高抵抗層の場合、電圧依存性が非常に大きいと
云う問題がある。When forming a high resistance layer such as a pull-down resistor on the same 8i substrate, conventionally, as shown in FIG. ! The film 12 is grown, masked with a resist film 13 or the like, and boron ions are implanted, for example, to form a P-swelled diffusion layer 14 to obtain the resistor. However, in the case of such a high resistance layer, there is a problem in that the voltage dependence is very large.
すなわち、第５図は、このような従来の拡散抵抗層に電
圧を印加した場合の拡散抵抗層内の空乏層の広がりを示
したものであるが、第５図からも明らかなように抵抗体
１４に電圧を印加した場合、特にｖｋｋ側の空乏層１５
の広がりが激しく、実質的な拡散層抵抗が大きくなる。In other words, FIG. 5 shows the spread of the depletion layer in the diffused resistance layer when a voltage is applied to such a conventional diffused resistance layer.As is clear from FIG. When a voltage is applied to 14, the depletion layer 15 on the vkk side in particular
spreads rapidly, and the effective diffusion layer resistance becomes large.
先に述べたようにプルダウン抵抗としては、数１００に
Ω程度必要であシ、又、高抵抗層を小さな領域に形成す
る必要から、抵抗層の濃度は低くしなければならず、こ
のことも、拡散抵抗層内の空乏層の広がりを大きくして
いる原因となっている。As mentioned earlier, the pull-down resistor requires several hundred ohms, and since it is necessary to form a high resistance layer in a small area, the concentration of the resistance layer must be low. , which causes the depletion layer in the diffused resistance layer to expand.
本発明の目的は、かかる、従来の高抵抗層の電圧依存性
を低減することＶＣある。An object of the present invention is to reduce the voltage dependence of such a conventional high resistance layer.
本発明は、抵抗領域のうち、基体との電位差が大きい側
を高濃度又は高深度としたことを特徴とする。The present invention is characterized in that the resistance region has a high concentration or a high depth on the side where the potential difference with the substrate is large.
以下、本発明を図面を使用して説明する。 Hereinafter, the present invention will be explained using the drawings.
第１図は、本発明の一実施例には高抵抗層でら夛、これ
は第２図に示すようにして形成される。FIG. 1 shows that one embodiment of the invention includes a high resistance layer, which is formed as shown in FIG.
すなわち、例えばＮ形Ｓｉ基板２１上に薄い酸化膜２２
を成長させ、その酸化膜２２に段差を設ける。その際に
、Ｖｋｋ側の酸化膜を薄くする。次Ｋ、この酸化膜２２
を通してレジスト膜３をマスクとして、例えはボロンを
イオン注入することにより、深さ方向に段差を持つ、Ｐ
膨拡散層２４を形成する。That is, for example, a thin oxide film 22 is formed on an N-type Si substrate 21.
is grown, and a step is provided in the oxide film 22. At that time, the oxide film on the Vkk side is made thinner. Next K, this oxide film 22
For example, by implanting boron ions through the resist film 3 as a mask, a P layer with steps in the depth direction is formed.
A swelling diffusion layer 24 is formed.
このようにして形成された拡散抵抗層２４に電圧を印加
した場合の拡散抵抗層２４側の空乏層２５の広がりは、
第１図に示すようになり、本実施例による拡散抵抗層２
４は、その抵抗値が、空乏層２５の広が夛の少い部分で
決定されるため、抵抗値の電圧依存性を少なくすること
ができる。When a voltage is applied to the diffused resistive layer 24 formed in this way, the spread of the depletion layer 25 on the diffused resistive layer 24 side is as follows:
As shown in FIG. 1, the diffused resistance layer 2 according to this embodiment
4, the resistance value is determined in a portion where the depletion layer 25 spreads less, so that the voltage dependence of the resistance value can be reduced.
以上のとおり、空乏層の広がシの大きな部分（電圧依存
性の大きな部分）の抵抗値を小さくすることＫよって、
抵抗層の電圧依存性を小さくすることができる。As mentioned above, by reducing the resistance value of the part where the depletion layer has a large spread (the part with large voltage dependence),
The voltage dependence of the resistance layer can be reduced.
第１図は本発明の一実施例を示す断面図、第２図は第１
図を形成するための断面図、第３図はＦＩＰ駆動用の出
力部の等価回路図、第４図は従来の抵抗層を形成するた
めの断面図、第５図は、第４図の従来例の電圧印加時の
空乏層の広がシを示す断面図である。
１・・・・・・ＰチャネルＭ０８ＦＢＴ（オープンドレ
イン）、２・・・・・・プルダウン抵抗、１１・・・・
・・Ｎ形番板、１２・・・・・・酸化膜、１３・・・・
・・レジスト膜、１４・・・・・・拡散抵抗層、２１・
・・・・・Ｎ形番板、２２・・・・・・酸化膜、２３・
・・・・・レジスト膜、２４・・・・・・拡散抵抗層、
２５・・・・・・空乏層。
代理人 弁理士 内 原 晋・ ”′・１１
。
°（−１
第 １ 図FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
3 is an equivalent circuit diagram of the output part for FIP drive, FIG. 4 is a sectional view for forming a conventional resistance layer, and FIG. 5 is a conventional FIG. 3 is a cross-sectional view showing the spread of a depletion layer when a voltage is applied in an example. 1...P-channel M08FBT (open drain), 2...Pull-down resistor, 11...
...N type number plate, 12... Oxide film, 13...
...Resist film, 14... Diffusion resistance layer, 21.
...N type number plate, 22... Oxide film, 23.
...Resist film, 24...Diffused resistance layer,
25...depletion layer. Agent Patent Attorney Susumu Uchihara・”′・11
. °(-1 Fig. 1
Claims (1)
、上記第２の導電形層を抵抗として使用する半導体装置
において、上記抵抗層のうち基板に対して高電位差の電
圧が印加される部分を高濃度又は高深度としたことを特
徴とする半導体装置。In a semiconductor device in which a second conductivity type layer is formed in a semiconductor portion of a first conductivity type and the second conductivity type layer is used as a resistor, a voltage with a high potential difference is applied to a substrate in the resistor layer. 1. A semiconductor device characterized by having a high concentration or high depth portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207467A JPS6185854A (en) | 1984-10-03 | 1984-10-03 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207467A JPS6185854A (en) | 1984-10-03 | 1984-10-03 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6185854A true JPS6185854A (en) | 1986-05-01 |
Family
ID=16540247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207467A Pending JPS6185854A (en) | 1984-10-03 | 1984-10-03 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185854A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184201A (en) * | 1989-06-07 | 1993-02-02 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Static induction transistor |
-
1984
- 1984-10-03 JP JP59207467A patent/JPS6185854A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184201A (en) * | 1989-06-07 | 1993-02-02 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Static induction transistor |
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