JPH0456492B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a programmable counter in which a memory section outputs "0" as preset data to a counter when an address where no data exists is selected.

Configuration of Conventional Example and Its Problems A conventional programmable counter in which a memory section outputs "0" to the counter as preset data will be described with reference to FIGS. 1 and 2. In FIG. 1, 1 is a clock terminal that supplies a clock to the counter 2, 3 is a preset terminal that supplies a preset signal to the counter 2, and 4 to 6 are address setting terminals of the address decoding section 7. .about.6 are connected to the A, B, and C terminals of the address decoding section 7, respectively. The counter 2 is composed of flip-flops 8 to 13 having a preset function, and in this example is a 6-bit binary down counter. flipflop 8-13
_C1 to _C6 are clock input terminals, _D1 to _D6 are preset data terminals, _Q1 to _Q5 are non-inverting output terminals, _PR1
~ _PR6 is a preset signal terminal. The address decoding section 7 determines the address of the memory section 14 according to inputs from the address setting terminals 4 to 6. The memory section 14 stores preset data for the counter 2. Output terminal of the memory section 14
PD ₁ ~ PD ₆ are flip-flops 8 ~ of counter 2
It is connected to 13 preset data terminals _D1 to _D6 . Address output terminals AD ₁ to AD 7 of the address decoding section ₇ are connected to address input terminals BD ₁ to _{BD 7} of the memory section 14 .

FIG. 2 is a specific configuration diagram of the address decoding section 7 and the memory section 14. The address decoding unit 7 consists of 7 addresses L ₁ to _{L 7} , and the “○” in each grid
The line output becomes high level when the marked bit goes low level. The unmarked bits are in a floating state, and the respective lines _L1 to _L7 are all pulled up.
The locations marked with "○" in each grid of the memory section 14 correspond to the inverters 15a inserted in the respective lines.
-15g becomes low level, and the input sides of the inverters 16a-16f of the bits marked with "O" become low level. The input sides of each of the inverters 16a to 16f are pulled up. Therefore, if any one of the "○" locations in each grid of bits in the memory section 14 becomes low level, the output of the inverter for that bit becomes high level. Note that 17a to 17c are inverters.

In the conventional programmable counter configured as described above, for example, the address decoding section 7
Address setting terminals 4 to 6 are displayed in binary as [000]
Then, on line _L1 , the output of line inverter 15a becomes low level, and the output terminal
The outputs of PD ₁ and PD ₃ become high level, and the preset data [000101] is output from the memory section 14 to the counter 2 from the MSB side to the LSB side as the preset data of the counter 2. Here, positive logic is used in which the low level is "0" and the high level is "1". After the preset data is output, when a preset signal is input to the preset terminal 3 of the counter 2,
Counter 2 selects the MSB according to the preset data.
From the side to the LSB side, it is set as [000101]. The counter 2 performs a counting operation from a preset count value in accordance with a clock input.
Furthermore, when the address setting terminals 4 to 6 of the address decoding section 7 are set to [010], the line _L3 is selected and is read from the memory section 14 as preset data.
Outputs [000000] to counter 2 from the MSB side to the LSB side. Furthermore, address decoding section 7
When address setting terminals 4 to 6 are [111],
Since all address lines _L1 ~ _L7 are not selected, inverter 1 of each address line _L1 ~ _L7
The outputs of 5a to 15g become high level, and the memory section 14 is stored from the MSB side as preset data.
Outputs [000000] toward the LSB side.

However, in the conventional configuration as described above, the memory is The unit 14 outputs "0". Therefore, address [010] is the same as an address where no ROM data exists. In digital integrated circuits,
Since the area occupied by the address decoding section 7 and the memory section 14 is large, the area must be kept to the minimum necessary. Furthermore, if there are more addresses than necessary, the element for driving the addresses will also need a large capacity, which will lead to an increase in chip area.

Purpose of the Invention The present invention solves the above-mentioned conventional drawbacks, and by reducing the number of addresses in the memory section that provides preset data to the counter, it is possible to reduce the area of the address decoding section and the area of the memory section. The purpose is to provide a programmable counter that can be used.

Structure of the Invention In order to achieve the above object, the programmable counter of the present invention includes: a counter having a preset function; a memory section that supplies preset data to this counter; and an address decoder section that selects an address of this memory section. a pull-up means for pulling up the data line of the memory section when the address signal is not output from the address decoding section; and a pull-up means for pulling up the data line of the memory section when the address signal is output from the address decoding section;
and an inverting means for inverting the output of the data line, and by outputting the output signal of the inverting means to the counter as preset data, The data part of the memory section whose setting data is "0" and the address part of the address decode section are deleted.

According to this configuration, the address part of the address decoding part and the data part of the memory part can be reduced, the area occupied by the address decoding part and the memory part in the integrated circuit can be reduced, and as a result, the chip area of the integrated circuit can be reduced. can be made smaller.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit block diagram of the main part of a programmable counter according to an embodiment of the present invention, FIG. 4 is a specific configuration diagram of an address decoding section and a memory section of the programmable counter, and FIGS. Components that are the same as those shown in are given the same reference numerals and their explanations will be omitted.

The difference between FIG. 3 and FIG. 1 is that the line connecting address output terminal AD ₃ of address decoding section 7 and address input terminal BD ₃ of memory section 14 has been deleted.

In FIG. 4, the line L ₃ for decoding the address AD ₃ of the address decoding unit 7 representing data "0" and the data selection line for selecting data by the inverter 15c and the address input terminal BD ₃ are deleted according to FIG. ing.

The operation of the programmable counter of this embodiment configured as described above will be explained below.
For example, address setting terminals 4 to 6 of the address decoding section 7 (represented by A, B, and C in FIG. 4)
If the input is [000] in binary representation, line _L1 will be selected. When line _L1 is selected, inverter 15a, which is the data line pull-down means,
Since the output of the memory section becomes low level, the data lines marked with "O" in the memory section become low level, and the other data lines become high level because they are pulled up by pull-up means (not shown). Therefore, preset data [000101] is output to the counter 2 from the MSB side to the LSB side. Then, when the preset signal is applied to the preset terminal 3, the counter 2
It is set to [000101] from the MSB side to the LSB side.

Next, when [010] or [111] is input in binary representation to the address setting terminals 4 to 6, the addresses [010] and [111] do not exist in the address decoding section 7, so the inverters 15a to 15a 15g
are all at a high level. Therefore, since the data line of the memory section 14 is pulled up by the pull-up means, when all the outputs of the address decoding section 7 are at high level, the inverter 16a
All input levels of ~16f become high level.
When the input levels of the inverters 16a to 16f all become high level, the output terminal PD ₁ of the memory section 14
~The output level of PD ₆ is all low level, that is, [000000]. As a result, the memory section 14 outputs preset data [000000] to the counter 2. When the address is [010], the setting data is [000000], so even if the address does not exist in the address decoding section 7, the set preset data is output to the counter 2. Therefore, even if the address whose setting data is "0" in the memory section 14 is deleted, the preset data can be obtained. Even at address [111], ROM is “0”
is output, but since no address such as [111] is specified, there is no problem.

Effects of the Invention As explained above, according to the present invention, since addresses whose setting data in the memory section is "0" are deleted from the address decoding section, the number of addresses in the memory section that supplies preset data to the counter can be reduced. Therefore, the area occupied by the address decoding section can be reduced. Furthermore, since the portion of the memory section that stores "0" can also be deleted, the area occupied by the memory section can also be reduced. As described above, since the area occupied by both the address decode section and the memory section can be reduced, the chip area of the integrated circuit can be reduced as a result.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of the main part of a conventional programmable counter, FIG. 2 is a specific configuration diagram of an address decoding section and a memory section of the same programmable counter, and FIG. 3 is a diagram of a programmable counter according to an embodiment of the present invention. FIG. 4, which is a circuit block diagram of the main part, is a specific configuration diagram of an address decoding section and a memory section of the same programmable counter. 2...Counter, 7...Address decoding section,
14...Memory section.

Claims (1)

[Claims] 1 A counter having a preset function, a memory section that supplies preset data to this counter, an address decoding section that selects the address of this memory section, and when an address signal is not output from the address decoding section, the address decoding section of the memory section a pull-up means for pulling up the data line;
and an inverting means for inverting the output of the data line of the memory section; The data part of the memory part and the address part of the address decoding part in which setting data of the memory part are all "0" are deleted, and the output signal of the inverting means is outputted to the counter as preset data. programmable counter.