JPH045685A - High resolution led panel display device - Google Patents

Abstract

PURPOSE:To transfer and display image data of high resolution by writing the image data in a storage part by th timing of a first clock, and reading it out of the storage part by the timing of a second clock, while a write processing is not being executed. CONSTITUTION:The control means is provided with a means for generating a first clock of the same frequency as a clock frequency of a data processor side and a means for generating a second clock whose frequency is different from the above frequency. In such a state, by counting a horizontal synchronizing signal, received image data is allocated to data storage part RAMs 3-1 - (n), and by the timing of a first clock, the image data is written in the storage parts 3-1 - (n). Also, in a period in which a write processing is not being executed, the image data is read out of the storage parts 3-1 - (n) by the timing of a second clock, and displayed on LED display units 5-1 - (n). This operation is executed in accordance with plural units divided by a display line, therefore, a noise and step out can be eliminated. In such a way, data of high resolution is read out and can be displayed on the units 5-1 - (n).

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 2] The present invention is an L
The present invention relates to a high resolution LED panel display device for displaying on an ED panel.

[Conventional technology]

Figure 5 shows image data from a data processing device such as a personal computer.
This is a diagram showing an outline of the configuration of the system displayed on the ED panel, in which 31 is the main body, 32 is the CRT display, 33 and 3.
6 is a power supply, 34 is a signal transfer unit, and 35 is an LED panel.

In recent years, graphics and animation techniques using computers have been used in a variety of fields.

Along with this, attempts have been made to display such image data on a large screen, and we have shown an overview of the configuration of a system that uses LED panels to configure a large screen and displays image data created on a personal computer in real time. is shown in Figure 5.

In the system shown in FIG. 5, image data created by a computer main body 31 such as a personal computer and displayed on a CRT display 32 has a high resolution of, for example, 640 dots x 400 lines. The display clock in this case uses a frequency of 21 MHz to 28 MHz. Therefore, in order to display this image data as it is on the LED panel 35 of the same resolution in real time, this 21
Image data, horizontal synchronization signals, and vertical synchronization signals are transferred in synchronization with a clock having a frequency of MHz to 28 MHz, and the LED panel 35 dynamically scans and displays image data using the clock. Note that the signal transfer unit 34 is for adjusting the signal level. With this kind of configuration, LED displays can be displayed on a large screen.
Panels are already commercially available.

[Problem to be solved by the invention]

However, in the conventional display method described above, dynamic scanning is performed by transferring a high-frequency clock of 21 MHz to 28 MHz together with image data, so there is an effect on the transfer line, causing the clock waveform to become dull.
There is a problem in that it is easily influenced by noise. As a result, synchronization is likely to occur, and noise and flickering due to synchronization become noticeable, making the image difficult to see. If the data transfer cable is lengthened, this problem becomes even more pronounced, resulting in a situation where data transfer becomes impossible and the screen disappears. Therefore, there is a problem in that the data transfer distance is limited and the LED panel cannot be placed at a greater distance from the computer system.

The present invention solves the above problems, and provides a high-resolution LED panel that can transfer and display high-resolution image data from the system to the LED panel without flickering by increasing the distance between the system and the LED panel. The purpose is to provide a display device.

[Means to solve the problem]

To this end, the present invention provides a high-resolution LED panel display device that receives high-resolution display data created by a data processing device together with a horizontal synchronization signal and a vertical synchronization signal and displays the data on an LED panel. LED panel consisting of a plurality of divided LED display units, said L
A plurality of storage means for storing display data corresponding to the ED panel, and a control means for writing image data received from the data processing device side into the storage means and reading out the stored image data and displaying it on the LED panel, The control means includes a clock generation means for generating a first clock having the same frequency as the clock frequency of the data processing device, and a clock generation means for generating a second clock having a frequency different from the first clock, and allocating the received image data to each storage means by counting the synchronization signals, and writing the image data to the storage means at the timing of the first clock;
During the period when the writing process is not performed, the image data is read from the storage means at the timing of the second clock, and the LE
It is characterized in that it is configured to be displayed on a D display unit.

[Two effects] In the high-resolution LED panel display device of the present invention, the LED panel is constituted by a plurality of LED display units divided into blocks according to the number of display lines, and storage means is provided correspondingly,
Since the control means generates a first clock having the same frequency as the clock frequency of the data processing device and a second clock having a frequency different from the first clock, the first clock is generated without using the clock from the data processing device. The image data can be written to the storage means using the clock, and the image data can be read out from the storage means and displayed on the LED display unit using the second clock. Therefore, the second clock frequency can be selected for display regardless of the first clock and the stored image data can be displayed, noise and loss of synchronization can be prevented, and screen flicker can be reduced.

〔Example〕

Examples will be described below with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of a high-resolution LED panel display device according to the present invention, and FIG. 2 is a diagram for explaining write control of a data storage unit. In the figure, 1 is a computer system, 2 is an SP converter, 3-1 to 3-n are data storage units, 4-1 to 4-n are PS converters, 5-1 to 5-n are LED units, 6 indicates a counter, and 7-1 to 7-25 indicate dip switches.

In FIG. 1, a computer system 1 is a data processing means consisting of a CPU main body, a graphic display, a keyboard, a mouse, etc., and an sp change section 2 processes serial image data transferred from the computer system 1, for example. The data is converted into 8-bit parallel data and output to the data storage units 3-1 to 3-n. L.E.
The D units 5-1 to 5-n are divided into blocks based on the number of display lines, and the data storage units 3-1 to 3-n are
It stores the corresponding image data for display. Therefore, for example, if 16 lines are one block for a display screen of 640 dots x 400 lines, each data storage section 3-1 to 3-n and LED unit 5-1 to 5-n each have a display screen of 640 dots x 16 lines. The configuration stores and displays image data, and n is 25.
becomes.

The PS conversion units 4-1 to 4-n are connected to the data storage units 3-1 to 3-3.
-n is converted into serial data and output to the LED units 5-1 to 5-n, and the LED units 5-1 to 5-n display this serial data.

Image data is written to and read from the data storage units 3-1 to 3-n as follows.

When serial image data, horizontal synchronization signals, and vertical synchronization signals are transferred from computer system 1, first,
The transfer line is reset by the vertical synchronization signal, and thereafter the number of lines is counted by the horizontal synchronization signal. And 1
Assuming that the block has 16 lines according to the previous example, the image data from the 1st line to the 16th line is transferred from the SP conversion unit 2 to the data storage unit 3 based on the count value of the number of lines.
-1 and write. Subsequently, when the 17th line is reached, it is switched to the data storage section 3-2 and image data is written in the same way, and thereafter, the 400th line,
Image data is written to the data storage section 3-n (25). When writing of image data up to the 400th line is completed, the same process is repeated from the first line using the vertical synchronization signal again.

The above switching control can be performed using a counter 6 for counting lines and dip switches 7-1 to 7-25 for setting count numbers for determining blocks as shown in FIG. The counter 6 is reset at the rise or fall of the vertical synchronization signal, and counts up at the rise or fall of the horizontal synchronization signal. When counting 400 lines,
It is sufficient to have a minimum of 9 bits of output from bit rOJ(bo) to bit r9J(b8). When one block is made up of 16 lines, the upper 5 bits excluding the lower 4 bits are used as a count value of the number of lines, and are used as a comparison signal with dip switches 7-1 to 7-25. Therefore, if dip switch 7-1 is set to ro 0000J, 7-2 is set to ``10000J'', 7-25 is set to ``11111'', the upper 5 pins) (b4 to b8) match only the dip switch 7-1. Then, when the 17th line is counted, there is a mismatch, but only the dip switch 7-2 matches, and when the 387th line is counted, only the dip switch 725 matches. In other words, the upper 5 bits of counter 6 (b4 to b8)
is compared with dip switches 7-1 to 7-25, and writing is selectively permitted to data storage units 3-1 to 3-n based on a match signal.

The data storage units 3-1 to 3-n write the image data output from the SP conversion unit 2 only while the above-mentioned write permission is granted, and read out the image data written asynchronously during other periods. Performs display processing. Therefore, the data storage units 3-1 to 3-n are used for writing processing for only 1/n of the data transfer time for one screen, and most of the other time is used for reading and displaying.

In other words, in the LED display units 5-1 to 5-n, the display is interrupted for 1/n of the data transfer time for one screen, but for most of the other time, the display is asynchronously repeated at an arbitrary frequency. can be processed.

FIG. 3 is a diagram showing an example of the configuration of a circuit that performs read/write control of a data storage section including a RAM, and FIG. 4 is a timing chart for explaining the relationship between vertical synchronizing signals, horizontal synchronizing signals, and data.

In FIG. 3, the falling detection circuit 11 detects a horizontal synchronizing signal H which is transferred together with image data from the system side.
3 is detected, the clock oscillator 2 is synchronized, and the counter 13 is cleared. The clock oscillator 12 generates a first clock of the same frequency as the image data transfer lock on the system side, for example, 21 MHz, and performs phase alignment using the fall detection signal of the horizontal synchronization signal H3. The counter 13 receives a horizontal synchronizing signal H
The comparator 14 compares this count value with a reference value and generates a data valid signal. That is, since the image data is transferred after a certain blanking period has elapsed with respect to the horizontal synchronizing signal H3 as shown in FIG. The comparator 14 detects that the blanking period has elapsed and generates a data valid signal. The sampling control circuit 15 starts controlling the SP converter 21 based on this data valid signal, and samples the image data at the timing of the first clock generated by the clock oscillator 12. The SP converter 21 converts serial data into, for example, 8-bit parallel data and outputs it. The timing signal wcK is transmitted from the sampling control circuit 15 to the read/write address control circuit 2.
Sent to 0. The above is the control system of the blade SP converter 21.

Further, the counter 16 is cleared by the vertical synchronizing signal S transferred from the system side together with the image data, similar to the horizontal synchronizing signal H5, and counts the horizontal synchronizing signal HS, that is, the number of lines, and the comparator 18 is The number of lines is compared with the set value of the dip switch 17. The clock oscillator 19 generates a second clock of an arbitrary frequency, for example, 2 MHz, completely independent of the first clock generated by the clock oscillator 12. The read/write address control circuit 20 enters a write mode when the comparator 18 matches, generates a write address and writes data, enters the read mode when the comparator 18 mismatches, and starts reading the data for which the read address was generated. It is something to do.

The signal used for the write timing is the timing signal WCK, and the signal used for the read timing is the second clock. Although the upper 4 bits of the counter 16 are not used for block determination as described above, they can be used commonly as a signal for the write line of each block, so the upper 4 bits of the counter 16 are not used for block determination. It goes without saying that it may be configured to be used as a line signal.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment, each dot is displayed on/off, but it may be configured so that blinking is controlled by the duty ratio and gradation display is performed for each pixel. In addition, the second clock used for reading is the same as the first clock used for writing on the system side.
Although the frequency of the clock is lowered, it is also possible to apply it to a system in which the first clock used for writing on the system side is lower than the frequency of the second clock. tsub
fD, in the case of a system with a slow data transfer rate, it is sufficient to match the clock frequency of the receiving side with the transfer lock without changing the clock frequency of the display side.

[Effect of Hathu]

As is clear from the above description, according to the present invention, an LED panel is configured with a plurality of units divided by display lines, and a clock of the same frequency as the image data transfer lock is applied to the storage memory corresponding to the unit. Since the image data is stored by synchronizing with the horizontal synchronization signal,
It is possible to eliminate noise and out-of-synchronization caused by problems in the transfer line, such as in conventional systems that also receive transfer locks from the system side. Moreover, since the data written to the storage memory is read out and displayed during a period other than the write period, the display clock can be selected completely independent of data transfer, and a clock with a frequency convenient for display can be used. . Therefore, the influence of noise on the transfer line can be eliminated, screen flicker can be significantly reduced, and the system and LED
The distance to the panel can be increased.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of a high-resolution LED panel display device according to the present invention, FIG. 2 is a diagram for explaining write control of a data storage section, and FIG. 3 is a data storage section equipped with a RAM. Figure 4 is a timing chart for explaining the vertical synchronization signal, horizontal synchronization signal, and data relationship, and Figure 5 is a diagram showing an example of the configuration of a circuit that performs read/write control of the FIG. 1 is a diagram showing an overview of the configuration of a system displayed on a panel. 1... Computer system, 2... SP conversion section,
3-1 to 3-n... data storage section, 4-1 to 4-n.
...PS conversion unit, 5-1 to 5-n... LED unit, 6... Counter, 7-1 to 7-25... Deep switch.

Claims (1)

[Claims] (1) Receive high-resolution display data created by a data processing device together with a horizontal synchronization signal and a vertical synchronization signal to display the LED
A high-resolution LED panel display device for displaying on a panel, the LED panel comprising a plurality of LED display units divided into blocks according to the number of display lines, a plurality of storage means for storing display data corresponding to the LED panel, and The storage means includes a control means for writing the image data received from the data processing device side and reading out the stored image data and displaying it on the LED panel, and the control means has a clock frequency that is the same as the clock frequency of the data processing device side. The apparatus includes a clock generating means for generating one clock and a clock generating means for generating a second clock having a frequency different from the first clock, and counts horizontal synchronizing signals and allocates received image data to each storage means, The image data is written to the storage means at the timing of the first clock, and the image data is read from the storage means at the timing of the second clock during a period when the writing process is not performed, and is displayed on the LED display unit. High resolution L featuring
ED panel display device.