JPH0457300A - Peak hold circuit - Google Patents

Abstract

PURPOSE:To exactly hold the peak of an input signal by forcedly dropping down a hold output voltage. CONSTITUTION:An input/output comparator 10 compares an input signal 1 and a hold output signal 3 and when the input signal is lower, an H input/output comparator signal 4 is outputted and supplied to an inverter 11 and a discharge control circuit 14. The inverter 11 inverts the signal 4 and outputs a charge siganal 5. When the input signal 1 is higher than a level signal 2, a level compa rator 13 outputs a level comparate signal 6. The circuit 14 outputs a discharge signal 7 which is made H with the rise of the signal 6 when the signal 4 is H and which is made L when the signal 4 is L. A hold circuit 12 increases a hold output voltage 3 by the signal 5 and decreases the voltage 3 by the signal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak hold circuit, and particularly to a peak hold circuit for an analog signal in which a sine wave is amplitude-modulated.

[Conventional technology]

Conventionally, this type of peak hold circuit has adopted a system in which when the input signal has a lower level than the hold output signal, the hold output signal is discharged by a resistor circuit.

[Problem to be solved by the invention]

The conventional peak hold circuit described above uses a resistor circuit to discharge the hold output signal, so if the input signal is lower than the discharge curve of the hold output signal, the hold signal will not drop to the peak of the input signal. Therefore, there is a drawback that the hold output signal becomes a higher voltage than the input signal.

[Means to solve the problem]

The peak hold circuit of the present invention includes a first comparator that compares an input signal and a peak hold output signal, a second comparator that compares the input signal and a level signal, and inverts the output of the first comparator. a discharge control circuit that generates a discharge signal from the output signals of the first comparator and the second comparator, and a hold circuit that generates the peak hold output signal from the output signal of the inverter and the discharge signal. It is composed of

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart diagram illustrating the operation of FIG. 1. Note that the symbols in the figure correspond to the symbols shown in FIG. 1, respectively. In FIGS. 1 and 2, the input/output comparator 10 compares the input signal 1 and the hold output signal 3, and when the input signal is low, outputs a high level input/output comparator signal 4, supply to. The inverter 11 inverts the input/output comparator signal 4 and applies a charge signal 5. Level comparator 13 outputs level comparison signal 6 when input signal 1 is higher than level signal 2. The discharge control circuit 14 outputs a discharge signal 7 which becomes high level at the rise of the level comparison signal 6 when the input/output comparison signal 4 is at a high level, and becomes low level when the input/output comparison signal 4 is at a low level. The hold circuit 12 increases the hold output voltage 3 with the charge signal 5 and decreases the hold output voltage 3 with the discharge signal 7.

〔Effect of the invention〕

As explained above, the peak hold circuit of the present invention has the effect of accurately holding the peak voltage of the input signal by forcibly lowering the hold output voltage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart diagram explaining the operation of FIG. 1. 1...Input signal, 2...Level signal,
3... Hold output signal, 4... Input/output comparator signal, 5... Charge signal, 6
...Level comparison signal, 7...
Discharge signal, 8... Input/output comparator, 11... Inverter, 12... Hold circuit, 13... Level comparator, 1
4...Discharge control circuit.

Claims (1)

[Claims] a first comparator that compares an input signal and a peak hold output signal; a second comparator that compares the input signal and a level signal; an inverter that inverts the output of the first comparator; A discharge control circuit that generates a discharge signal from the output signal of the comparator and the second comparator, and a hold circuit that generates the peak hold output signal from the output signal of the inverter and the discharge signal. peak hold circuit.