JPH0457431A - Clock synchronizing system - Google Patents

Abstract

PURPOSE:To realize a constant and short synchronization time by adopting a clock synchronizing system of a pseudo open loop type in which a clock phase estimate device and a broad band PLL are combined. CONSTITUTION:A first half section of the system comprising an envelope detection means 3, a sine wave generating means 4, a phase correlation detection means 5, a low pass filter 6 and a reverse tangent calculation means 7 traces clock phase fluctuation by the additional provision of a PLL comprising a phase comparator 9, a subtractor 10 and a digital VCO 11 to estimate a phase of a modulation clock through its open loop configuration. However, the gain of the PLL is high, then its noise band width is sufficiently wider than a band width of the low pass filter 6. Thus, the S/N of the recovered clock is depending only on the band width of the low pass filter and the PLL is regarded equivalently as an open loop from the entire system.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides clock synchronization for obtaining demodulated samples synchronized with a modulation clock in a receiver of a digital communication system using amplitude phase shift (APSK) modulation. Regarding the method.

(Prior Art) Conventionally, as a clock synchronization method for amplitude phase shift (APSK) signals, a phase locked loop (P) as shown in FIG.
L L ) have been widely used. The operation will be briefly explained below with reference to the drawings. In the figure, thin lines indicate real signals, and thick lines indicate orthogonal signals.

In order to sample the APSK signal at a timing synchronized with the modulation clock, the A/D converter 13 inputs the signal obtained by quasi-synchronous orthogonal demodulation of the APSK signal, and modulates the input signal based on the sample clock. N samples are taken every cycle. The clock phase error detection means 14 is
A digital time series signal quantized to the number of bits j (Il is a positive integer) by the /D converter 13 is input, and a phase error between the sample clock and the modulation clock is detected.

The clock phase error detection means 14 uses a method of comparing the phases of a sample clock and an extracted clock component, a method of calculating a clock phase error from samples of signal points and zero crossing points, and the like. The loop filter 15 averages the phase errors detected by the clock phase error detection means 14.

The digital VCO 16 is phase-controlled by the output of the loop filter 15 and reproduces a clock synchronized with the modulation clock. This becomes the sample clock for the A/D converter 13.

(Problem to be solved by the invention) The above is an overview of the conventional clock synchronization method.

This method basically uses PLL, so PLL
There are unique synchronization issues. That is, synchronization takes time, and the synchronization time varies greatly depending on the phase of the initial sample.

Additionally, hang-up occurs due to π phase shift. Furthermore, delays in channel filters and the like existing in the loop affect the characteristics.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a pseudo open-loop clock synchronization method that achieves constant and short synchronization time.

(Means for Solving the Problem) The clock synchronization method of the present invention has an amplitude phase shift (APSK)
) is a clock synchronization method in which the signal is sampled at a timing synchronized with the modulation clock.

an oscillator that outputs a clock with a frequency approximately N (N is a positive integer) times the modulation clock; and an A/D converter that performs quasi-synchronous orthogonal demodulation of the APSK signal and samples the demodulated signal with the output clock of the oscillator. And the number of bits by the A/D converter! an envelope detection means for inputting a quantized digital time series signal to calculate the envelope of the digital time series signal; sine wave generating means for outputting orthogonal signals consisting of mutually orthogonal sine waves having a frequency of /H, and detecting the correlation between the phase of the output signal of the envelope detection means and the phase of the output signal of the sine wave generating means a low-pass filter for averaging the outputs of the phase-correlation detecting means; and an arctangent calculation means for inputting orthogonal signals that are mutually orthogonal signals output from the low-pass filter and calculating the arctangent thereof. a frequency divider that divides the output clock of the oscillator by 1/H; a phase comparator that compares the phase of the output signal of the frequency divider with the phase of the synchronous clock; a subtracter that takes the difference between the phase and the phase of the output signal of the arctangent calculation means; and a subtracter that calculates the phase of the synchronous clock that is the output signal based on the clock phase error that is the output of the subtracter. A sample of modulated clock timing is extracted from among the output samples of the A/D converter using a digital phase controlled oscillator (VCO) controlled in periodic steps and the timing of the synchronized clock which is an output signal of the digital VCO. It is equipped with a sampler.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, thin lines indicate real signals, and thick lines indicate orthogonal signals.

In the clock synchronization method shown in Fig. 1, the amplitude phase deviation (A
In order to sample the PSK signal at a timing synchronized with the modulation clock, a clock synchronized with the modulation clock is generated. The oscillator 1 outputs a clock whose frequency is approximately N (N is a positive integer) times the modulation clock. The A/D converter 2 samples a signal obtained by quasi-synchronous orthogonal demodulation of the APSK signal using the output clock of the oscillator 1. The envelope detection means 3 inputs the digital time series signal quantized to the number of bits 1 (" is a positive integer) by the A/D converter 2,
Calculate the envelope of the digital time series signal.

The sine wave generating means 4 generates 1/H of the output clock of the oscillator 1.
outputs orthogonal signals consisting of mutually orthogonal sine waves having frequencies of .

The sine wave generating means 4 includes a counter that counts the output clock of the oscillator 1, and an R register that is accessed by using the output of the counter as an address and in which the value of the sine wave is written in advance.
This can be easily realized using an OM table. The phase correlation detection means 5 detects the correlation between the phase of the output signal of the envelope detection means 3 and the phase of the output signal of the sine wave generation means 4. Here, if the frequency of the output clock of the oscillator 1 is f8, the period is T, (-1/f,), and the output of the envelope detection means 3 is x(,T,), then the phase correlation detection means 5
The output Y (IT,) is Y <,,T, > =X (,lT, )exp (
−j 2yr(f,/N), T, ) (n=o, 1.2...). The low-pass filter 6 averages the output of the phase correlation detection means 5. The arctangent calculation means 7 inputs the orthogonal signal that is the output of the low-pass filter 6, calculates its tangent, and outputs the phase difference between the modulation clock and the sine wave of frequency f. On the other hand, the frequency divider 8 divides the output clock of the oscillator 1 by 1/H. A phase comparator 9 compares the phase of the output signal of the frequency divider 8 and the phase of the synchronization clock.The output clock of the frequency divider 8 and the original clock of the synchronization clock, which is the output of the digital VCO II, are both connected to the oscillator 1. Since the output clock is 2, the phase of the output signal of the phase comparator 9 is 2.
It is an integral multiple of π/N. The subtracter 10 calculates the difference between the phase of the output signal of the phase comparator 9 and the phase of the output signal of the arctangent calculation means 7.

The digital VCO II controls the phase of the synchronized clock to be output based on the clock phase error that is the output of the subtracter 10 in cycle steps of the output clock of the oscillator 1. The sampler 12 extracts a sample of the modulated clock timing from among the output samples of the A/D converter 2 using the synchronized clock timing that is the output of the digital C011.

In FIG. 1, the first half consisting of an envelope detection means 3, a sine wave generation means 4, a phase correlation detection means 5, a low-pass filter 6, and an arctangent calculation means 7 estimates the phase of the modulated clock by open looping. ing. Generally, the deviation in the frequency of the modulated clock in the transmitter and receiver is very small, so in short packet communication systems, the phase of the modulated clock is estimated more than once at initial synchronization, etc., and then estimated over the entire packet period. A method can be adopted in which data is determined using the phase of the modulated clock. However, in a communication system that handles continuous signals, slow fluctuations in the clock phase occur due to frequency shifts of modulated clocks in the transmitter and receiver, so it is necessary to deal with this. Therefore, in the present invention, a PLL consisting of a phase comparator 9, a subtracter 10, and a digital vC011 is added to track the clock phase fluctuation. This PL
Since L has a high gain, its noise bandwidth is sufficiently wide compared to the bandwidth of the low-pass filter 6. Therefore, the S/N ratio of the recovered clock depends only on the bandwidth of the low-pass filter 6, and the entire system can be equivalently regarded as an open loop.

In the present invention, since the clock for A/D converting the input signal and the sample clock of the sampler are asynchronous, an asynchronous connection is required. In FIG. 1, A/D converter 2
, the envelope detection means 3, the sine wave generation means 4, the phase correlation detection means 5, and the low-pass filter 6 perform repetitive processing at the period T of the output clock of the oscillator 1, the arctangent calculation means 7, and the phase comparator 9. , the subtracter 10, the digital vC011, and the sampler 12 are the digital VCO11.
The period T of the synchronous clock which is the output of The process is repeated. Here, an asynchronous connection is made between the low-pass filter 6 and the arctangent calculation means 7, but this does not pose a problem since the period Tc is an integral multiple of the period T.

(Effects of the Invention) As explained above, in the present invention, a constant and short synchronization time can be achieved by adopting a pseudo open-loop clock synchronization method that combines a clock phase estimator and a wideband PLL. . Furthermore, continuous phase tracking is possible even with respect to clock frequency errors. Furthermore, since it is entirely digital, it can be expected to have effects such as no adjustment, easy integration into an IC, and software processing using a digital signal processor (DSP).

Envelope detection means, 4... Sine wave generation means, 5...
- Phase correlation detection means, 6... low pass filter, 7.
... Arctangent calculation means, 8 ... Frequency divider, 9 ... Phase comparator, 10 ... Subtractor, 11.16 ... Digital C0112 ... Sampler, 14 ... Clock phase Error detection means, 15... loop filter.

Claims (1)

[Claims] In a clock synchronization method in which an amplitude phase shift signal is sampled at a timing synchronized with a modulation clock, an oscillator that outputs a clock having a frequency approximately N (N is a positive integer) times the modulation clock; an A/D converter that performs quasi-synchronous orthogonal demodulation and samples the demodulated signal with the output clock of the oscillator; and a digital time series quantized into a number of bits l (l is a positive integer) by the A/D converter. envelope detection means for inputting a signal and calculating an envelope of the digital time-series signal; and an orthogonal signal for inputting an output clock of the oscillator and having a frequency of 1/N of the output clock and consisting of mutually orthogonal sine waves. , a phase correlation detection means for detecting the correlation between the phase of the output signal of the envelope detection means and the phase of the output signal of the sine wave generation means, and averaging the output of the phase correlation detection means. an arctangent calculating means for inputting orthogonal signals which are outputs of the low-pass filter and calculating the arctangent thereof; and a frequency divider for dividing the output clock of the oscillator by 1/N. a phase comparator that compares the phase of the output signal of the frequency divider with the phase of the synchronization clock, and a phase comparator that compares the phase of the output signal of the frequency divider with the phase of the synchronization clock; a digital phase controlled oscillator that controls the phase of the synchronized clock, which is an output signal, in cycle steps of the output clock of the oscillator based on the clock phase error that is the output of the subtracter; and the digital phase controlled oscillator. a sampler that extracts a sample of modulated clock timing from among the output samples of the A/D converter using the timing of the synchronized clock that is an output signal of the A/D converter.