JPH0457432A - Clock synchronizing system - Google Patents

Abstract

PURPOSE:To realize a constant and short synchronization time by adopting a clock synchronizing system of a pseudo open loop type in which a clock phase estimate device and a broad band PLL are combined. CONSTITUTION:An A/D converter 2, an envelope detection means 3, a sine wave generating means 4, a phase correlation detection means 5, and a low pass filter 6 make repetitive processing for a period Ts of an output clock of an oscillator 1, and a tangent calculation means 7, a phase comparator 9, a subtractor 10 and a digital VCO 11, an adder 12 and an interpolation means 13 make repetitive processing for a period Tc of a synchronizing clock being an output of the digital VCO 11. Thus, the pseudo open loop type clock synchronizing system realizing a constant and short synchronization time is offered.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides clock synchronization for obtaining demodulated samples synchronized with a modulation clock in a receiver of a digital communication system using amplitude phase shift (APSK) modulation. Regarding the method.

(Prior Art) Conventionally, as a clock synchronization method for amplitude phase shift (APSK>signal), a phase locked loop (PL) as shown in Fig. 2 has been used.
L) has been widely used. The operation will be briefly explained below with reference to the drawings. In the figure, thin lines indicate real signals, and thick lines indicate orthogonal signals.

In order to sample the APSK signal at a timing synchronized with the modulation clock, the A/D converter 14 inputs the signal obtained by quasi-synchronous orthogonal demodulation of the APSK signal, and modulates the input signal based on the sample clock. N samples are taken every cycle. The clock phase error detection means 15 is
A digital time series signal quantized to a bit number Q (fJ is a positive integer) is input to the /D converter 14, and a phase error between the sample clock and the modulation clock is detected.

The clock phase error detection means 15 uses a method of comparing the phases of a sample clock and an extracted clock component, a method of calculating a clock phase error from samples of signal points and zero crossing points, and the like. The loop filter 16 averages the phase errors detected by the clock phase error detection means 15.

The digital VC017 is phase-controlled by the output of the loop filter 16 and reproduces a clock synchronized with the modulation clock. This becomes the sample clock for the A/D converter 14.

(Problem to be solved by the invention) The above is an overview of the conventional clock synchronization method.

This method basically uses PLL, so PLL
There are unique synchronization issues. That is, synchronization takes time, and the synchronization time varies greatly depending on the phase of the initial sample.

Additionally, hang-up occurs due to π phase shift. Furthermore, delays in channel filters and the like existing in the loop affect the characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pseudo open-loop clock synchronization method that achieves constant and short synchronization time.

(Means for Solving the Problem) The clock synchronization method of the present invention has an amplitude phase shift (APSK)
) is a clock synchronous method in which the signal is sampled at a timing synchronized with the modulation clock, and the signal is sampled at a timing that is approximately N of the modulation clock.
(N is a positive integer) times the frequency of an oscillator; an A/D converter that performs quasi-synchronous quadrature demodulation of the APSK signal and samples the demodulated signal with the output clock of the oscillator; The number of bits j! by the D converter! envelope detection means for inputting a quantized digital time-series signal (Il is a positive integer) and calculating an envelope of the digital time-series signal; sine wave generating means for outputting orthogonal signals consisting of mutually orthogonal sine waves having a frequency of /H, and detecting the correlation between the phase of the output signal of the envelope detection means and the phase of the output signal of the sine wave generating means a low-pass filter for averaging the outputs of the phase-correlation detecting means; and an arctangent calculation means for inputting orthogonal signals that are mutually orthogonal signals output from the low-pass filter and calculating the arctangent thereof. and a frequency divider that divides the output clock of the oscillator by 1/H.

a phase comparator that compares the phase of the output signal of the frequency divider and the phase of the synchronization clock; and a subtracter that takes the difference between the phase of the output signal of the phase comparator and the phase of the output signal of the arctangent calculation means. and a digital phase control oscillator (VCO) that controls the phase of the synchronized clock, which is an output signal, in period steps of the output clock of the oscillator based on the clock phase error that is the output of the subtracter, and the output of the digital VCO. an adder that adds the output signal of the subtracter to the signal to obtain more accurate interpolation timing synchronized with a modulation clock;
and interpolation means for inputting the output of the A/D converter and performing interpolation processing at the output timing of the adder to obtain a sample of the modulation clock timing.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, thin lines indicate real signals, and thick lines indicate direct exchange signals.

In the clock synchronization method shown in Fig. 1, the amplitude phase deviation (A
In order to sample the PSK signal at a timing synchronized with the modulation clock, a clock synchronized with the modulation clock is generated. The oscillator 1 outputs a clock whose frequency is approximately N (N is a positive integer) times the modulation clock. The A/D converter 2 samples a signal obtained by quasi-synchronous orthogonal demodulation of the APSK signal using the output clock of the oscillator 1. The envelope detection means 3 inputs the digital time series signal quantized to the number of bits of 1 (1 is a positive integer) by the A/D converter 2,
Calculate the envelope of the digital time series signal.

The sine wave generating means 4 generates 1/H of the output clock of the oscillator 1.
outputs orthogonal signals consisting of mutually orthogonal sine waves having frequencies of . The sine wave generating means 4 can be easily realized by a counter that counts the output clock of the oscillator 1 and a ROM table that is accessed using the output of the counter as an address and in which the value of the sine wave is written in advance. The phase correlation detection means 5 detects the correlation between the phase of the output signal of the envelope detection means 3 and the phase of the output signal of the sine wave generation means 4. Here, the frequency of the output clock of oscillator 1 is f
,,T for the light period.

(-1/f, binding, if the output of the envelope detector ¥9.3 is x(,T,), then the output Y of the phase correlation detector 5
(,'r', ) is Y(.T, )=X <nT, )exa 4-j 2
It is expressed as π(f, , /N), T, ) (n=0.1, 2...). The low-pass filter 6 averages the output of the phase correlation detection means 5. The arctangent calculation means 7 inputs the orthogonal signal that is the output of the low-pass filter 6, calculates its arctangent, and outputs the phase difference between the modulation clock and the sine wave of frequency f. On the other hand, the frequency divider 8 divides the output clock of the oscillator 1 by 1/H. The phase comparator 9 compares the phase of the output signal of the frequency divider 8 and the phase of the synchronous clock. Since the output clock of the frequency divider 8 and the original clock of the synchronous clock which is the output of the digital VCO II are both the output clock of the oscillator 1, the phase of the output signal of the phase comparator 9 is 2.
It is an integral multiple of π/N. The subtracter 10 calculates the difference between the phase of the output signal of the phase comparator 9 and the phase of the output signal of the arctangent calculation means 7.

The digital VCO II controls the phase of the synchronized clock to be output based on the clock phase error that is the output of the subtracter 10 in cycle steps of the output clock of the oscillator 1. Adder 12 adds the output signal of subtracter 10 to the output signal of digital VCOII to obtain more advanced interpolation timing synchronized with the modulation clock. The interpolation means 13 performs interpolation processing using several samples near the output timing of the adder 12 from among the output samples of the A/D converter 2 to obtain samples of modulation clock timing.

In FIG. 1, the first half consisting of an envelope detection means 3, a sine wave generation means 4, a phase correlation detection means 5, a low-pass filter 6, and an arctangent calculation means 7 estimates the phase of the modulated clock by open looping. ing. Generally, the deviation in the frequency of the modulated clock in the transmitter and receiver is very small, so in short packet communication systems, the phase of the modulated clock is estimated more than once at the time of initial synchronization, and then estimated over the entire packet period. A method can be used in which data is determined using the phase of a modulated clock. However, in a communication system that handles continuous signals, a shift in the frequency of the modulated clock in the transmitter/receiver causes slow clock phase fluctuations, so it is necessary to deal with this. Therefore, in the present invention, a PLL consisting of a phase comparator 9, a subtracter 10, and a digital C011 is added to track the clock phase fluctuation. However, since this PLL has a high gain, its noise bandwidth is sufficiently wide compared to the bandwidth of the low-pass filter 6. Therefore, the S/N ratio of the recovered clock depends only on the bandwidth of the low-pass filter 6. , the entire system can be considered isometrically open loop.

In the present invention, since the clock for A/D converting the input signal and the clock for outputting the interpolated sample are asynchronous,
Requires an asynchronous connection. In FIG. 1, an A/D converter 2, an envelope detection means 3, a sine wave generation means 4, a phase correlation detection means 5, and a low-pass filter 6 are connected to an oscillator 1.
The process is repeated with the period T of the output clock of the arctangent calculation means 7, the phase comparator 9, the subtractor 101. The digital VCO II, the adder 12 and the interpolation means 13 are
Period T of the synchronous clock that is the output of the digital VCOII. The process is repeated. Here, an asynchronous connection is made between the low-pass filter 6 and the arctangent calculation means 7, but this does not pose a problem because the period T is an integral multiple of the period T.

(Effect of the invention) The above is the explanation 1. As described above, in the present invention, by adopting a pseudo open-loop clock synchronization method that combines a clock phase estimator and a wideband PLL, it is possible to realize a constant and short synchronization time, and it is possible to achieve continuous synchronization even against clock frequency errors. This enables accurate phase tracking. Furthermore, since the samples of the modulation clock timing are obtained by interpolation processing, the number of samples per modulation period can be reduced. Furthermore, since it is entirely digital, it can be easily integrated into an IC without any adjustment, and can be expected to perform software processing using a digital signal processor (DSP).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional clock synchronization system. 1... Oscillator, 2.14... A/D converter, 3...
・Envelope detection means, 4...Sine wave generation means, 5
... phase correlation detection means, 6 ... low pass filter,
7... Arctangent calculation means, 8... Frequency divider, 9... Phase comparator, 10... Subtractor, 11.17... Digital vCO512... Adder, 13... interpolation means,
15... Clock phase error detection means, 16... Loop filter.

Claims (1)

[Claims] In a clock synchronization method in which an amplitude phase shift signal is sampled at a timing synchronized with a modulation clock, an oscillator that outputs a clock having a frequency approximately N (N is a positive integer) times the modulation clock; an A/D converter that performs quasi-synchronous orthogonal demodulation and samples the demodulated signal with the output clock of the oscillator; and a digital time series quantized into a number of bits l (l is a positive integer) by the A/D converter. envelope detection means for inputting a signal and calculating an envelope of the digital time-series signal; and an orthogonal signal for inputting an output clock of the oscillator and having a frequency of 1/N of the output clock and consisting of mutually orthogonal sine waves. , a phase correlation detection means for detecting the correlation between the phase of the output signal of the envelope detection means and the phase of the output signal of the sine wave generation means, and averaging the output of the phase correlation detection means. an arctangent calculating means for inputting orthogonal signals which are outputs of the low-pass filter and calculating the arctangent thereof; and a frequency divider for dividing the output clock of the oscillator by 1/N. a phase comparator that compares the phase of the output signal of the frequency divider with the phase of the synchronization clock, and a phase comparator that compares the phase of the output signal of the frequency divider with the phase of the synchronization clock; a digital phase controlled oscillator that controls the phase of the synchronized clock, which is an output signal, in cycle steps of the output clock of the oscillator based on the clock phase error that is the output of the subtracter; and the digital phase controlled oscillator. an adder that adds the output signal of the subtracter to the output signal of the A/D to obtain more accurate interpolation timing synchronized with the modulation clock;
1. A clock synchronization system, comprising: interpolation means for inputting the output of a converter and performing interpolation processing at the output timing of the adder to obtain samples of modulated clock timing.