JPH0457480A - Clamp circuit - Google Patents

Abstract

PURPOSE:To remove clamp error from an output signal and to enable a clamp operation with high accuracy by connecting a buffer circuit to be used for the clamp operation and a current supply circuit for deciding the operational current of the buffer circuit through a resistor, and setting the current value of the current supply circuit by the same clamp operation as the buffer circuit. CONSTITUTION:Transistors 20 and 23 are respectively operated as first and second buffer circuits 40 and 41 of an emitter follower, and a transistor 21, resistor 15, capacitor 12, transistor 22, resistor 16 and capacitor 13 are respectively connected to the inputs of those two buffer circuits 40 and 41 so as to constitute first and second switching circuits 42 and 43 for fixing the input potentials of the buffer circuits 40 and 41 respectively at a prescribed potential only during a prescribed period. On the other hand, a sample and-hold circuit 44 is composed of a capacitor 14 and a switch circuit 25, and a transistor 24 and a resistor 18 are operated as a current supply circuit 45 which current value is changed corresponding to the signal of the sample-and-hold circuit 44.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clamp circuit for performing DC reproduction in video signal processing for high-visibility televisions, video cameras, and the like.

[Prior Art] Fig. 5 is a configuration diagram showing a conventional clamp circuit, in which (1) is an input terminal, (2) and (3) are capacitors, (4) and (5) are resistors, ([i), (7) are transistors, and (8) is an output terminal.

Next, the operation of the above configuration will be explained.

A video signal is input from an input terminal (1) through a capacitor (2) to an emitter follower composed of a transistor (6) and a resistor (5). In addition, the transistor (7
), a resistor (4), and a capacitor (3) (these constitute a switching circuit, and the transistor (7) becomes conductive when the clamp pulse (cp) becomes a high potential.
The potential of the base of transistor (6) is approximately (v cp)
The normal clamp pulse (cp), which is fixed at
cp).

[Problems to be Solved by the Invention] Conventional clamp circuits are configured in one or more ways, so if noise is included in the video signal during the clamp period, the noise level is clamped and the black level of the video signal is reduced. This invention was made to solve the above-mentioned problems, such as the presence of holes in each scanning line.
The object of the present invention is to provide a clamp circuit that can reliably fix the DC level of a video signal.

[Means for Solving the Problems] A clamp circuit according to the present invention connects a buffer circuit used for clamp operation and a current source circuit that determines its operating current via a resistor, and The present invention is characterized in that the current value of the source circuit is set by the same clamping operation as the buffer circuit.

[Function] According to the present invention, the current source circuit is set in a clamp operation, and the current value corresponds to the potential held by the sample and hold circuit, and the error of the clamp operation is converted into a current value, and the current source circuit and , and the first pan 77 circuit to convert it into a voltage, and the error is removed from the output voltage.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a configuration diagram of a clamp circuit according to an embodiment of the present invention, in which (1) is an input terminal, (10)
, (11), (12), (+3), (14) are capacitors (+5), (16), (+7), (+8), (19)
is the resistance, (20), (21).

(22), (23), (24) are transistors, (2
5) is a switch circuit, and (8) is an output terminal.

The above transistor (20) and transistor (23)
are the first and second 472 emitter followers, respectively.
The transistor (21), the resistor (15), the capacitor (12) and the transistor (22), the resistor (1B), and the capacitor (13) operate as 7 circuits (40) and (41). ), (41)
buffer circuits (40) for a predetermined period of time.

(41) First and second switching circuits (421, (431) each identifying the human power potential to a predetermined potential.
It consists of a capacitor (I4) and a switch circuit (
25) constitute a sample and hold circuit (44), and the transistor (241 and resistor (18) operate as a current source circuit (45) whose current value changes according to the signal of this sample and hold circuit (44), This current source circuit (4
The collector of the transistor (24) of 5) and the emitter of the transistor (2υ) of the first buffer circuit (40) are connected via a resistor (19).

Next, Fi;i:! The operation of the configuration will be explained with reference to the second M. Note that in the following description, transistors (201, (211, (221, +231,
+241 Novase'Itffi is small to F-minute;
It is also assumed that the change in base-emitter voltage with respect to collector current is sufficiently small.

First, consider an input signal in which no noise is included in the horizontal blanking period shown in FIG. 2 fA) and the level of that portion is VIN. When using the pulse shown in Figure 2 (Bl) as the clamp pulse (CPI), the transistor (21) becomes conductive when the clamp pulse (cp) becomes a high potential, and the potential of the base of the transistor (20) is fixed at VCPI. and the capacitor (10) is V IN
It is charged with a potential difference of -V CPI. Even if the clamp pulse (cp) becomes low potential and the transistor (21) is cut off, the charge charged in the capacitor (10) is retained, and the base signal waveform of the transistor (20) becomes as shown in Fig. 2 (C). It becomes like this.

Similarly, the waveform of the signal of the transistor (23) becomes a waveform clamped to VCP2, as shown in FIG. 2(D). The switch circuit (25) is connected when the clamp pulse (cp) is at a high potential, and the emitter potential of the transistor (23) at that time VCP2-
Even if VBEI Taekwonde 7 t (14) is charged, the clamp pulse becomes a low potential, and the switch circuit (25) is cut off, the capacitor (14) maintains the potential of the base of the transistor (24) as shown in Fig. 2 ( As shown in E), it is held at VCP2-VBEI.

Then, the transistor (24) causes the transistor (
20) The current flowing through 4m is (VCP2-VBEI-
VBE3)/R18, and the output waveform of the output terminal (8) is the signal waveform of the emitter of the transistor (20) (a waveform that is lower than the base signal waveform by VBE2).
From resistance f1911m voltage drop (VCP2-VB
The waveform obtained by subtracting El-VIIE3')X R19/R18 is as shown in FIG. 2 (G).

Next, a case where noise is included in the horizontal blanking period will be explained with reference to FIG.

When noise is added during the horizontal blanking shown in Figure 3 (Al), the clamping operation is performed using the impedance through which the human input signal is transmitted and V CP as shown in Figure 3 (^).
l, V The impedance of the power supply of CF2, and the transistor (201° (21)
Since the impedance of is not completely zero, the fixed potentials V CPl, V C
There may be cases where it cannot be clamped to F2, and for example, the signal waveform at the base of the transistor (20) may have an error [col, (C1l) as shown in FIG. 3 (C1).

At this time, also at the base of the transistor (23),
Similar error (eel) as in FIG. 3(D).

(all) occurs, and since they have the same circuit configuration, eO, eol, and elbell occur. In addition, the output of the sample-and-hold circuit (44), that is, the signal waveform of the base of the transistor (24), is an extraction of the error e01, all of the clamp operation, as shown in FIG. 3(E). . This error is the transistor (2
4) is converted into a current, and an error component is generated in the voltage drop by the resistor (19).

Here, if the resistance value R19 of the resistor (18) and the resistance value R18 of the resistor (18) are set to R19=R18, the voltage drop caused by the resistor (19) L, : is eol (= e
O), e 11 (z e l ), and the clamp error (eO,
el) is canceled by the voltage drop across the resistor (19),
At the output terminal (8), a signal with ramp errors removed is obtained as shown in FIG. 3(F).

FIG. 4 is a configuration diagram of a clamp circuit according to another embodiment of the present invention, in which (30) and (31) are the first
and the second,<Zuffa circuit (40), (41) and the first
and the second switching circuits (42) and (43), respectively. According to this embodiment, when the clamping characteristics are made soft, the inserted resistor (3
0) and (31), resistor (18) and resistor (19)
) is adjusted so that the same amount of voltage drop as the clamp error occurring at the base of the transistor (20) occurs at the resistor (19), the same effect as in the above embodiment can be obtained.

Further, the transistor used in the first embodiment may be an NPN type, a PNP type, or a field effect transistor, and the same effects as in the above embodiment can be achieved.

[Effects of the Invention] Hereinafter, as shown in L, according to the present invention, the buffer circuit used for clamp operation and the current source circuit that determines the operating current are connected via a resistor, and the current of the current source circuit is Since the value is set using the same clamp operation as the buffer circuit described above, the same voltage drop as the error that occurs during clamp operation occurs in the resistor connecting the 4777 circuit and the current source, eliminating the clamp error from the output signal. It is possible to perform a highly accurate clamping operation.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a clamp circuit according to an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams of various parts for explaining the operation of an embodiment of the present invention, and FIG. 4 is a diagram of the clamp circuit according to the invention. FIG. 5 is a block diagram showing a clamp circuit according to another embodiment of the present invention, and FIG. 5 is a block diagram showing a conventional clamp circuit. (10)・-: I7 capacitor, (tS), , resistance, (
40), (41) -...4727 circuit, (42),
(43)...Switching circuit, (44)...Sample hold circuit, (45)...Current source circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A first to which a video signal is applied via a capacitor;
two second buffer circuits, first and second switching circuits that are connected to the inputs of the two buffer circuits and fix the input potentials of the buffer circuits to predetermined potentials for a predetermined period; It consists of a sample hold circuit connected to the output of the second buffer circuit, and a current source circuit whose current value changes according to the output of the sample hold circuit, and the first buffer circuit and the current source circuit are connected to at least A clamp circuit characterized in that the circuit is connected through one resistor.