JPH0457923U - - Google Patents
Info
- Publication number
- JPH0457923U JPH0457923U JP1990099908U JP9990890U JPH0457923U JP H0457923 U JPH0457923 U JP H0457923U JP 1990099908 U JP1990099908 U JP 1990099908U JP 9990890 U JP9990890 U JP 9990890U JP H0457923 U JPH0457923 U JP H0457923U
- Authority
- JP
- Japan
- Prior art keywords
- level
- pulse
- circuit
- outputs
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図及び第２図はそれぞれ本考案の一実施例
の回路図及びこの実施例の動作を説明するための
各部信号の波形図、第３図及び第４図、第５図は
それぞれ従来のタイマ用集積回路の一例の回路図
及びこのタイマ用集積回路の動作、課題を説明す
るための各部信号のの波形図である。
１……微分回路、２……基準電圧発生回路、３
……トリガ用コンパレータ、４……しきい値用コ
ンパレータ、５……フリツプフロツプ、６……放
電用トランジスタ、１０，１０Ａ……タイマ用集
積回路、２０……時定数回路、Ｃ１，Ｃ０１……
コンデンサ、Ｒ１〜Ｒ５，Ｒ０１……抵抗。
Figures 1 and 2 are a circuit diagram of an embodiment of the present invention and waveform diagrams of various signals for explaining the operation of this embodiment, and Figures 3, 4, and 5 are diagrams of conventional circuits, respectively. 1 is a circuit diagram of an example of a timer integrated circuit, and waveform diagrams of signals of various parts for explaining the operation and problems of this timer integrated circuit. 1...Differential circuit, 2...Reference voltage generation circuit, 3
...Trigger comparator, 4...Threshold comparator, 5...Flip-flop, 6...Discharge transistor, 10, 10A...Timer integrated circuit, 20...Time constant circuit, C1, C01 ...
Capacitor, R1 to R5, R01 ...Resistance.
Claims (1)
力する微分回路と、第１及び第２の基準電圧を発
生する基準電圧発生回路と、前記微分回路の出力
が前記第１の基準電圧を越えると所定のレベルに
なるセツトパルスを出力するトリガ用コンパレー
タと、抵抗及びコンデンサを備えて電源端子及び
接地端子との間に設けられ、レベルが時間に応じ
て変化する時定数信号を発生する外部接続の時定
数回路からの前記時定数信号のレベルが前記第２
の基準電圧を越えると所定のレベルになるリセツ
トパルスを出力するしきい値用コンパレータと、
前記セツトパルスによりセツトされて第１のレベ
ルとなり前記リセツトパルスによりリセツトされ
て第２のレベルとなる出力パルスの出力するフリ
ツプフロツプ回路と、前記出力パルスのレベルに
応じてオン・オフし前記時定数回路のコンデンサ
の充放電を制御するトランジスタとを有すること
を特徴とするタイマ用集積回路。 a differentiating circuit that differentiates and outputs a trigger pulse input from the outside; a reference voltage generating circuit that generates first and second reference voltages; and when the output of the differentiating circuit exceeds the first reference voltage, A trigger comparator that outputs a set pulse with a level of The level of the time constant signal from the circuit is
a threshold comparator that outputs a reset pulse that reaches a predetermined level when the reference voltage of
A flip-flop circuit outputs an output pulse that is set to the first level by the set pulse and is reset to the second level by the reset pulse; 1. A timer integrated circuit, comprising: a transistor for controlling charging and discharging of a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990099908U JPH0457923U (en) | 1990-09-25 | 1990-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990099908U JPH0457923U (en) | 1990-09-25 | 1990-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0457923U true JPH0457923U (en) | 1992-05-19 |
Family
ID=31842165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990099908U Pending JPH0457923U (en) | 1990-09-25 | 1990-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0457923U (en) |
-
1990
- 1990-09-25 JP JP1990099908U patent/JPH0457923U/ja active Pending
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