JPH0457925U - - Google Patents
Info
- Publication number
- JPH0457925U JPH0457925U JP10075090U JP10075090U JPH0457925U JP H0457925 U JPH0457925 U JP H0457925U JP 10075090 U JP10075090 U JP 10075090U JP 10075090 U JP10075090 U JP 10075090U JP H0457925 U JPH0457925 U JP H0457925U
- Authority
- JP
- Japan
- Prior art keywords
- auto
- input
- zero circuit
- input voltage
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は従来のオートゼロ回路の一例を示す回路図、
第３図は第２図の動作を説明するタイミングチヤ
ート、第４図は入力系統のスイツチとしてＪ−Ｆ
ＥＴを用いた場合の回路図、第５図は第４図の動
作波形図である。
１……入力端子、２……Ｒ−Ｃフイルタ、３…
…入力電圧系統スイツチ、４……アンプ、５……
アース系統スイツチ、６……Ａ／Ｄ変換器、７…
…ＣＰＵ、１７……光絶縁型ＭＯＳスイツチ。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing an example of a conventional auto-zero circuit.
Fig. 3 is a timing chart explaining the operation of Fig. 2, and Fig. 4 is a J-F switch as an input system switch.
A circuit diagram when ET is used, FIG. 5 is an operating waveform diagram of FIG. 4. 1...Input terminal, 2...R-C filter, 3...
...Input voltage system switch, 4...Amplifier, 5...
Earth system switch, 6... A/D converter, 7...
...CPU, 17...Optical isolation type MOS switch.
Claims (1)
して交互に入力するように構成されたオートゼロ
回路において、 前記入力電圧系統に、光絶縁型のＭＯＳスイツ
チを設けたことを特徴とするオートゼロ回路。[Claims for Utility Model Registration] An auto-zero circuit configured to alternately input an input voltage and a ground voltage via switches, characterized in that an optically isolated MOS switch is provided in the input voltage system. Auto zero circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10075090U JPH0457925U (en) | 1990-09-26 | 1990-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10075090U JPH0457925U (en) | 1990-09-26 | 1990-09-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0457925U true JPH0457925U (en) | 1992-05-19 |
Family
ID=31843638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10075090U Pending JPH0457925U (en) | 1990-09-26 | 1990-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0457925U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843042B2 (en) * | 1977-06-24 | 1983-09-24 | 小橋工業株式会社 | Cultivating claws |
| JPS6479999A (en) * | 1987-09-22 | 1989-03-24 | Takamisawa Cybernetics | Sample and hold circuit |
-
1990
- 1990-09-26 JP JP10075090U patent/JPH0457925U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843042B2 (en) * | 1977-06-24 | 1983-09-24 | 小橋工業株式会社 | Cultivating claws |
| JPS6479999A (en) * | 1987-09-22 | 1989-03-24 | Takamisawa Cybernetics | Sample and hold circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0457925U (en) | ||
| JPS6340899U (en) | ||
| JPS60169989U (en) | data acquisition circuit | |
| JPS6236146Y2 (en) | ||
| JPH0373073U (en) | ||
| JPS62146320U (en) | ||
| JPH02128418U (en) | ||
| JPH0193837U (en) | ||
| JPH02126417U (en) | ||
| JPS62114538U (en) | ||
| JPS6456021U (en) | ||
| JPS6172933U (en) | ||
| JPS6381515U (en) | ||
| JPS6286739U (en) | ||
| JPH0178428U (en) | ||
| JPH02120935U (en) | ||
| JPS63117128U (en) | ||
| JPH0253638U (en) | ||
| JPS62155524U (en) | ||
| JPH01138110U (en) | ||
| JPS58122197U (en) | Multi-point measuring device | |
| JPH042110U (en) | ||
| JPS62191300U (en) | ||
| JPS5885833U (en) | Input switching circuit | |
| JPS6424599U (en) |