JPH0459475U

JPH0459475U -

Info

Publication number: JPH0459475U
Application number: JP10140890U
Authority: JP
Priority date: 1990-09-27
Filing date: 1990-09-27
Publication date: 1992-05-21

Description

[Brief explanation of the drawing]

第１図は本考案に係るピーク検出回路の一実施
例を示す構成図、第２図は動作を説明するための
タイムチヤート、第３図は従来のピーク検出回路
の一例を示す構成図、第４図および第５図は入力
波形と出力波形の関係を示す図である。１……ＡＤ変換器、３……メモリ、１０……最
大値を検出する回路、２０……最小値を検出する
回路、１１，２１，１２，２３……ラツチ、１３
，２３……デジタルコンパレータ、３０……コン
トローラ。 FIG. 1 is a block diagram showing an embodiment of a peak detection circuit according to the present invention, FIG. 2 is a time chart for explaining the operation, and FIG. 3 is a block diagram showing an example of a conventional peak detection circuit. 4 and 5 are diagrams showing the relationship between input waveforms and output waveforms. 1... AD converter, 3... Memory, 10... Circuit for detecting maximum value, 20... Circuit for detecting minimum value, 11, 21, 12, 23... Latch, 13
, 23... digital comparator, 30... controller.

Claims

[Claims for Utility Model Registration] An AD converter that converts an analog input signal to digital; a first stage latch that holds the output of the AD converter; and the output of the AD converter and the output of the first stage latch. A digital comparator outputs a signal for holding the output of the AD converter in the first stage latch when the output of the AD converter is larger, and after the comparison by this digital comparator, the first stage latch outputs a signal for holding the output of the AD converter. a circuit for detecting the maximum value, comprising a second stage latch that holds the value held in the latch; a first stage latch that holds the output of the AD converter; a digital comparator that compares the outputs of the latches in the first stage and outputs a signal for holding the output of the AD converter in the first stage latch if the output of the AD converter is smaller; a circuit for detecting the minimum value, comprising a second stage latch which holds the value held in the first stage latch after the comparison; an output of the second stage latch of the circuit for detecting the maximum value; A memory for storing the output of the second-stage latch of the circuit for detecting a value, and a controller for controlling the timing of holding in each of the second-stage latches and the timing of storing in the memory; In the peak detection circuit that detects the maximum value and minimum value for each time, the controller is configured such that the maximum value or minimum value detected first by determining the outputs of the two digital comparators is stored in the memory first. A peak detection circuit characterized in that it is configured to have a function of controlling the storage order.