JPH0459782B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit, and particularly to a complementary type integrated circuit.
The present invention relates to semiconductor memories and semiconductor integrated circuits having MOS circuits (CMOS circuits).

[Prior art]

The first CMOS memory cell circuit has a complementary MOS structure (CMOS structure), and the memory cell is composed of MOS transistors of the same conductivity type in the same well.
Figure 2 shows a schematic cross-sectional view of the same CMOS structure. In Figure 1, 13 to 16 are n channels.
MOSFET, 17, 18 are high resistance polysilicon,
19, 20 are storage nodes, 10 is a word line, 1
1 and 12 are data lines. In Figure 2, 1
is an n-type Si substrate, and the p-channel MOSFET is 4,
The p-type high-concentration impurity regions 5 and 6 are formed as a drain and a source, respectively, and a gate. The n-channel MOSFET is formed in p-type well 2 with n-type high concentration impurity regions 7 and 8 serving as a drain and source, respectively, and 9 serving as a gate. Connect 6 and 9 as input terminals, and
By connecting , 4 as an output terminal, 4 as a power supply terminal, and 8 as a ground terminal, a CMOS inverter circuit can be constructed, which is used as the main component of the memory peripheral circuit section. On the other hand, the memory cell is constituted by MOSFETs in p-type well 3, with n-type high concentration impurity regions 21, 22, and 23 serving as drains or sources and 24 and 25 serving as gates. 27
25 is a word line, and 26 is a data line. The n-type high concentration impurity region 22 serves as a storage node and corresponds to 19 and 20 in FIG.

Incidentally, it has been pointed out that α particles emitted from impurities in the memory package material cause soft errors in the CMOS static RAM as well, which has become a problem. For example, when α particles are irradiated from above the memory cell, electron-hole pairs are generated in the p-type well 3 along the trajectory 28 of the α particles. When the storage node is at a high voltage level, the generated electrons 29
It flows into the n ⁺ diffusion layer and lowers the voltage level of the same node, causing malfunction (soft error).

[Purpose of the invention]

The present invention prevents such malfunctions.
It concerns a CMOS structure, and its key point is to reduce the collection efficiency with which electrons (or holes) excited by alpha particles are collected at storage nodes.

[Summary of the invention]

In order to reduce collection efficiency, the present invention forms an n ⁺ diffusion layer 31 in the well of the storage node, and forms the well surface 32 as shown in FIG.
It is characterized by forming a p ⁺ layer 33 in the well at a deeper portion than the p ⁺ layer, and having a p layer 34 adjacent to and below the p + layer in the well. Electrons excited by alpha particles, 35 storage nodes,
The inflow to 31 is at the boundary between the p ⁺ layer and the p layer, 3
This can be effectively prevented by the potential barrier formed at 6. At this time, the impurity concentration ratio between the p ⁺ layer and the p layer is 10 ² or more. In this structure p ⁺
Since there is a p-layer adjacent to and below the p-layer, by making the p-layer sufficiently thick, it is possible to simultaneously make the well deep and to make the depth of the boundary between p ⁺ -p layers as shallow as possible. Increasing the depth of the well means increasing the base width of the parasitic bipolar transistor consisting of regions 7, 2, and 1 in Figure 2, and as a result, the transistor's base width increases.
h _FE can be reduced. This is area 7, 2, 1 in Figure 2.
Transistors and regions 5, 1, 2 formed in
This has the effect of preventing the start-up (latch-up) of the operation of the thyristor, which is made up of transistors formed in the . On the other hand, by making the depth of the p ⁺ -p layer boundary 36 shallower, the proportion of electrons generated along the track 37 of α particles that are reflected by the potential barrier at the boundary 36 increases. , As a result, collection efficiency can be reduced.
Furthermore, in the present invention, since the p ⁺ layer is formed deeper than the well surface, the threshold voltage can be optimized by controlling the impurity concentration in the channel forming portion of the MOS transistor.

[Embodiments of the invention]

A first embodiment of the present invention will be described below with reference to FIG. The difference between Figure 3 and Figure 2 is that n-type Si
P-type well (depth ~5 μm) formed on the substrate, 38
A p ⁺ layer 33 is formed within the layer.
A method for forming this p ⁺ layer will be described below.

As shown in FIG. 4, after diffusing the p-well 42, a SiO ₂ layer 46 and a photoresist layer 45 are applied on the Si surface, a window is opened in the desired area, and boron ions are heated through the window. Energy is applied to form the p ⁺ layer, 43. If the implantation energy is 150KeV, the depth R _P ~0.42μm,
A p ⁺ layer with a layer thickness of ~0.16 μm can be achieved. The ratio of impurity concentration between the p ⁺ layer and the p-type well is preferably 10 ² or more. After ion implantation, laser light is irradiated to restore the crystallinity of the p-type Si surface layer while maintaining the dose distribution (laser annealing). If irradiated with 1000MW ruby laser light, the depth from the surface will be 0.3 ~
Crystallinity in a 0.5 μm region can be restored.

In this way, the p ⁺ layer 43 can be formed in a portion deeper than the surface of the p-type well 42 (depth: 0.4 μm). Furthermore, in the present invention, the p layer below the p ⁺ layer is made sufficiently thick, and the p well depth is set to 5 μm, so that latch-up is extremely difficult to occur.

A second embodiment of the present invention will be explained with reference to FIG. In FIG. 5, 51 is an n-type Si substrate;
The channel MOSFET uses p-type high concentration impurity regions 52 and 53 as the drain and source, respectively.
54 as a gate. n channel
The MOSFET has 56,
The n-type high concentration impurity regions 57 are formed as a drain and source, respectively, and 58 is formed as a gate. 54, 58 are connected as input terminals, 53,
Connect 56 to output terminal, 52 to power supply terminal, 57
If it is set as a ground terminal, a CMOS inverter circuit can be constructed and used as the main component of the memory peripheral circuit section. In the well 55,
The p ⁺ layer 59 is formed deeper than the well surface to prevent α particle-induced noise electrons from flowing into the peripheral circuit section. On the other hand, the memory cell is a p-type well 60
It is constituted by a MOS type field effect transistor in which n-type high concentration impurity regions 61, 62, and 63 serve as drains or sources, and 64 and 65 serve as gates. Here, in the well 60, p ⁺
The storage node 62 is formed by forming the layer 66 slightly deeper than the well surface and shallower than the p ⁺ layer 59.
This prevents alpha particle-induced noise electrons from entering.
In addition, in this embodiment, the n ⁺ diffusion layer of the storage node, 6
Since the p ⁺ layer 66 is formed in contact with the storage node 2, the capacitance C _P of the storage node increases, and soft errors are less likely to occur. On the other hand, n
The type high impurity concentration region 56 is located in the p-type well 55.
Since there is no substantial contact with the p ⁺ layer 59, an increase in the capacitance of this drain is prevented and the memory peripheral circuit section can be operated at high speed. 67 is a high resistance polysilicon, 65 is a word line, and 63 is a data line. The manufacturing method for the p ⁺ layers 66 and 59 is the same as in the first embodiment. If the implantation energy when forming the p ⁺ layer 66 by implanting boron ions is 90 KeV, a p ⁺ layer 66 with R _P ~0.27 μm and a layer thickness of 0.13 μm can be realized. p ⁺ layer 59
When forming by boron ion implantation, assuming the implantation energy is 150KeV, R _P ~
A p ⁺ layer of 0.42 μm and a layer thickness of ~0.16 μm, 59 can be realized.

That is, since the P-type well region 55 for the memory peripheral circuit section on the right side of the embodiment in FIG. 5 is generally formed by impurity diffusion, the concentration distribution of P-type impurities due to impurity diffusion in the P-type well region 55 is as shown in FIG. As shown by a curve 55, the distribution decreases monotonically from the surface of the semiconductor substrate toward the inside.

On the other hand, since the P-type high concentration impurity semiconductor layer 59 inside the P-type well region 55 for the memory peripheral circuit section is generally formed by ion implantation,
The concentration distribution of the P-type high concentration impurity semiconductor layer 59 is shown in FIG.
As shown by a curve 59, the distribution has a peak inside the semiconductor substrate.

Therefore, the P-type impurity concentration distribution in the P-type well region 55 after ion implantation for forming the P-type high concentration impurity semiconductor layer 59 is the distribution 5 due to impurity diffusion.
5 and the distribution 59 due to ion implantation is added to form a curve Lp.

As shown in FIG. 7, the P-type impurity concentration distribution obtained by adding the P-type well region 60 and the P-type high-concentration impurity semiconductor layer 66 in the memory cell portion becomes Lp, and the drain/source region 6 of the MOS transistor
The concentration distribution of impurities 1, 62, and 63 is Ln61,
62, 63, a fairly high concentration P-type high concentration impurity semiconductor layer is in contact with the PN junction at depth Xj, and the memory cell storage node is
- A large node capacitance is formed by the P+ junction,
It can be understood that soft errors are less likely to occur.

On the other hand, the distribution of N-type impurities in the drain/source regions 56, 57 of the MOS transistor for the memory peripheral circuit section is shown by curves Ln56, 57 in FIG.
As shown in the figure, the drain/source region 5
6, 57 and the P-type well region 55 is located at depth Xj in FIG.
As shown by the shaded part of the curve Lp in Figure 6, the high-concentration impurity semiconductor layer is essentially non-contact with the junction, so it is difficult to implant ions to create the high-concentration impurity semiconductor layer. Therefore, although the concentration of the P-type impurity semiconductor layer of the PN junction at Xj increases slightly, the increase in the parasitic capacitance of the MOS transistor due to this is slight, and it can be understood that the decrease in the operating speed of the peripheral circuit is suppressed.

〔Effect of the invention〕

As described above, the present invention forms the n ⁺ diffusion layer (depth ~0.3 μm) of the storage node of the memory cell in the well, and forms the p ⁺ layer in the well deeper than the well surface. (depth ~ 0.4 μm), and a p layer (thickness ~ 0.4 μm) in the well adjacent to and below this p ⁺ layer.
4.6 μm). The effects of this structure are as follows. This structure has a p ⁺ layer in the shallow part of the well and a sufficiently thick p layer below it, so α
The efficiency with which electrons excited by particles flow into storage nodes (collection efficiency) can be sufficiently reduced, and latch-up is extremely unlikely to occur. Furthermore, since the P ⁺ layer is formed deeper than the well surface, the impurity concentration in the channel forming portion of the MOS transistor can be kept at a low value and the threshold voltage can be optimized.

Therefore, it is extremely useful as an element structure of the CMOS static RAM having strong α resistance according to the present invention.

[Brief explanation of the drawing]

Fig. 1 is a CMOS memory cell circuit diagram, Fig. 2 is a schematic cross-sectional view of the same CMOS structure, Fig. 3 is a diagram showing the element structure of a CMOS static RAM according to an embodiment of the present invention, and Fig. 4 is a diagram of the CMOS memory cell circuit diagram. It is a figure which shows the manufacturing method example of an Example. FIG. 5 shows another embodiment of the invention.
Diagram showing the element structure of CMOS static RAM,
6 and 7 are diagrams showing impurity concentration distributions in the memory peripheral circuit section and memory cell section of the embodiment of FIG. 5. 38, 51... n ⁺ type substrate, 52, 53... p ⁺
Layer, 54, 58, 64...Gate electrode, 55, 6
0, 34...p-type well, 56, 57, 61, 6
3...n ⁺ layer, 31, 62... storage node.

Claims (1)

[Claims] 1. A source and a drain are formed in a surface region of a second conductivity type well provided in a semiconductor substrate having a first conductivity type semiconductor region by a first conductivity type high concentration impurity region. a high concentration impurity semiconductor layer of a second conductivity type and containing impurities at a higher concentration than the well, in the well at a portion deeper than the surface of the substrate; a second conductivity type semiconductor layer in a well adjacent to and below the impurity semiconductor layer; the memory MOS transistor formed in the second conductivity type well constitutes a memory cell; The high concentration impurity semiconductor layer is formed in the well so as to be in contact with the high concentration impurity region of the first conductivity type that becomes the source or drain of the memory MOS transistor, and It has a MOS transistor for the memory peripheral circuit section whose source and drain are formed by another high concentration impurity region of the first conductivity type in the surface region of the two conductivity type well, and has a higher concentration than the high concentration impurity semiconductor layer. Further, in the other well in a deeper portion, another high concentration impurity semiconductor layer of a second conductivity type and containing an impurity at a higher concentration than the other well is provided, and in the other well, the semiconductor layer is provided with another high concentration impurity semiconductor layer, and in the other well, the semiconductor layer is provided with another high concentration impurity semiconductor layer containing an impurity at a higher concentration than the other well. A semiconductor device characterized in that the other high-concentration impurity semiconductor layer is formed so as to be substantially non-contact with the source or drain of the MOS transistor for a circuit section.