JPH0459939U - - Google Patents

Info

Publication number
JPH0459939U
JPH0459939U JP1990103254U JP10325490U JPH0459939U JP H0459939 U JPH0459939 U JP H0459939U JP 1990103254 U JP1990103254 U JP 1990103254U JP 10325490 U JP10325490 U JP 10325490U JP H0459939 U JPH0459939 U JP H0459939U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
land
electrode
insulating substrate
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990103254U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990103254U priority Critical patent/JPH0459939U/ja
Publication of JPH0459939U publication Critical patent/JPH0459939U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の係るハイブリツドＩＣの要部
平面図、第２図は第２実施例を示す同要部平面図
である。第３図は一般的はハイブリツドＩＣの斜
視図、第４図は同要部平面図である。 １……絶縁基板、２……半導体ペレツト、２ａ
……電極パツド、５……搭載ランド、９……導電
接着材、１０……ワイヤ（金属細線）、１３……
リード、１３ａ……基端部、１６……配線パター
ン、１６ａ……電極取出し部、１８……電極ボン
デイングランド（ステツチランド）。 FIG. 1 is a plan view of the main parts of a hybrid IC according to the present invention, and FIG. 2 is a plan view of the main parts showing a second embodiment. FIG. 3 is a perspective view of a typical hybrid IC, and FIG. 4 is a plan view of the main part thereof. 1...Insulating substrate, 2...Semiconductor pellet, 2a
... Electrode pad, 5 ... Mounting land, 9 ... Conductive adhesive, 10 ... Wire (thin metal wire), 13 ...
Lead, 13a... Base end portion, 16... Wiring pattern, 16a... Electrode extraction portion, 18... Electrode bonding land (stitch land).

Claims (1)

【実用新案登録請求の範囲】 １ 半導体ペレツトの搭載ランドの近傍に、先端
部が搭載ランドから離隔した電極ボンデイングラ
ンドを有する配線パターンを絶縁基板上に形成し
、絶縁基板の周辺部近傍に多数のリードを配設し
て、上記搭載ランド上に導電接着材を介して半導
体ペレツトをマウントし、金属細線にて上記半導
体ペレツトの電極パツドと電極ボンデイングラン
ドおよび上記配線パターン電極取出し部とリード
をワイヤボンデイングし、電気的に接続したハイ
ブリツドＩＣにおいて、 上記電極ボンデイングランドの配置を千鳥状に
し、かつ、形状を菱形に形成したことを特徴とす
るハイブリツドＩＣ。 ２ 半導体ペレツトの搭載ランドの近傍に、先端
部が搭載ランドから離隔した電極ボンデイングラ
ンドを有する配線パターンを絶縁基板上に形成し
、絶縁基板の周辺部近傍に多数のリードを配設し
て、上記搭載ランド上に、導電接着材を介して半
導体ペレツトをマウントし、金属細線にて上記半
導体ペレツトの電極パツドと電極ボンデイングラ
ンドおよび上記配線パターン電極取出し部とリー
ドをワイヤボンデイングし、電気的に接続したハ
イブリツドＩＣにおいて、 上記リードの基端部の配置を千鳥状にし、かつ
、形状を菱形に形成したことを特徴とするハイブ
リツドＩＣ。[Claims for Utility Model Registration] 1. A wiring pattern having an electrode bonding land whose tip end is separated from the mounting land is formed on an insulating substrate near the mounting land of the semiconductor pellet, and a large number of wires are formed near the periphery of the insulating substrate. Arrange the leads, mount the semiconductor pellet on the mounting land via a conductive adhesive, and wire-bond the electrode pad of the semiconductor pellet to the electrode bonding land and the electrode extraction part of the wiring pattern to the lead using a thin metal wire. In the electrically connected hybrid IC, the electrode bonding lands are arranged in a staggered manner and have a rhombic shape. 2. A wiring pattern having an electrode bonding land whose tip end is separated from the mounting land is formed on an insulating substrate near the mounting land of the semiconductor pellet, and a large number of leads are arranged near the periphery of the insulating substrate. A semiconductor pellet was mounted on the mounting land via a conductive adhesive, and the electrode pad of the semiconductor pellet and the electrode bonding land and the electrode extraction part of the wiring pattern and the lead were wire bonded with a thin metal wire to electrically connect. A hybrid IC characterized in that the base end portions of the leads are arranged in a staggered manner and have a rhombic shape.
JP1990103254U 1990-09-28 1990-09-28 Pending JPH0459939U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990103254U JPH0459939U (en) 1990-09-28 1990-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990103254U JPH0459939U (en) 1990-09-28 1990-09-28

Publications (1)

Publication Number Publication Date
JPH0459939U true JPH0459939U (en) 1992-05-22

Family

ID=31848059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990103254U Pending JPH0459939U (en) 1990-09-28 1990-09-28

Country Status (1)

Country Link
JP (1) JPH0459939U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100954A (en) * 2001-09-26 2003-04-04 Citizen Watch Co Ltd Resin-sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100954A (en) * 2001-09-26 2003-04-04 Citizen Watch Co Ltd Resin-sealed semiconductor device

Similar Documents

Publication Publication Date Title
JPH0459939U (en)
JPH0125973Y2 (en)
JPH038449U (en)
JPH0313752U (en)
JPS62166640U (en)
JPS61173191U (en)
JP2000077559A (en) Semiconductor device
JPS646038U (en)
JPS6418738U (en)
JPH01174949U (en)
JPS61153374U (en)
JPH01115237U (en)
JPS60118242U (en) IC chip package
JPS6161833U (en)
JPS60136145U (en) IC chip package
JPH0365275U (en)
JPS6338350U (en)
JPH0320450U (en)
JPH01145138U (en)
JPS5965553U (en) integrated circuit device
JPH0343732U (en)
JPS6416636U (en)
JPH0249133U (en)
JPH0213731U (en)
JPS59121841U (en) Package for IC chip