JPH0459939U - - Google Patents

Info

Publication number
JPH0459939U
JPH0459939U JP1990103254U JP10325490U JPH0459939U JP H0459939 U JPH0459939 U JP H0459939U JP 1990103254 U JP1990103254 U JP 1990103254U JP 10325490 U JP10325490 U JP 10325490U JP H0459939 U JPH0459939 U JP H0459939U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
land
electrode
insulating substrate
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990103254U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990103254U priority Critical patent/JPH0459939U/ja
Publication of JPH0459939U publication Critical patent/JPH0459939U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の係るハイブリツドICの要部
平面図、第2図は第2実施例を示す同要部平面図
である。第3図は一般的はハイブリツドICの斜
視図、第4図は同要部平面図である。 1……絶縁基板、2……半導体ペレツト、2a
……電極パツド、5……搭載ランド、9……導電
接着材、10……ワイヤ(金属細線)、13……
リード、13a……基端部、16……配線パター
ン、16a……電極取出し部、18……電極ボン
デイングランド(ステツチランド)。

Claims (1)

  1. 【実用新案登録請求の範囲】 1 半導体ペレツトの搭載ランドの近傍に、先端
    部が搭載ランドから離隔した電極ボンデイングラ
    ンドを有する配線パターンを絶縁基板上に形成し
    、絶縁基板の周辺部近傍に多数のリードを配設し
    て、上記搭載ランド上に導電接着材を介して半導
    体ペレツトをマウントし、金属細線にて上記半導
    体ペレツトの電極パツドと電極ボンデイングラン
    ドおよび上記配線パターン電極取出し部とリード
    をワイヤボンデイングし、電気的に接続したハイ
    ブリツドICにおいて、 上記電極ボンデイングランドの配置を千鳥状に
    し、かつ、形状を菱形に形成したことを特徴とす
    るハイブリツドIC。 2 半導体ペレツトの搭載ランドの近傍に、先端
    部が搭載ランドから離隔した電極ボンデイングラ
    ンドを有する配線パターンを絶縁基板上に形成し
    、絶縁基板の周辺部近傍に多数のリードを配設し
    て、上記搭載ランド上に、導電接着材を介して半
    導体ペレツトをマウントし、金属細線にて上記半
    導体ペレツトの電極パツドと電極ボンデイングラ
    ンドおよび上記配線パターン電極取出し部とリー
    ドをワイヤボンデイングし、電気的に接続したハ
    イブリツドICにおいて、 上記リードの基端部の配置を千鳥状にし、かつ
    、形状を菱形に形成したことを特徴とするハイブ
    リツドIC。
JP1990103254U 1990-09-28 1990-09-28 Pending JPH0459939U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990103254U JPH0459939U (ja) 1990-09-28 1990-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990103254U JPH0459939U (ja) 1990-09-28 1990-09-28

Publications (1)

Publication Number Publication Date
JPH0459939U true JPH0459939U (ja) 1992-05-22

Family

ID=31848059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990103254U Pending JPH0459939U (ja) 1990-09-28 1990-09-28

Country Status (1)

Country Link
JP (1) JPH0459939U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100954A (ja) * 2001-09-26 2003-04-04 Citizen Watch Co Ltd 樹脂封止型半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100954A (ja) * 2001-09-26 2003-04-04 Citizen Watch Co Ltd 樹脂封止型半導体装置

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