JPH0313752U - - Google Patents
Info
- Publication number
- JPH0313752U JPH0313752U JP1989075932U JP7593289U JPH0313752U JP H0313752 U JPH0313752 U JP H0313752U JP 1989075932 U JP1989075932 U JP 1989075932U JP 7593289 U JP7593289 U JP 7593289U JP H0313752 U JPH0313752 U JP H0313752U
- Authority
- JP
- Japan
- Prior art keywords
- land
- lead
- mounting land
- out wiring
- hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案に係るハイブリツドＩＣの要部
平面図、第２図は流れ止め部の変形例を示す要部
拡大平面図である。第３図は従来のハイブリツド
ＩＣの斜視図、第４図は同じく要部拡大平面図で
ある。
２……半導体ペレツト、５……搭載ランド、９
……導電接着材、１６……配線パターン、１７…
…引出し線、１７ａ……流れ止め部、１８……電
極ボンデイングランド（ステツチランド）、１８
ａ……先端部。
FIG. 1 is a plan view of the main part of a hybrid IC according to the present invention, and FIG. 2 is an enlarged plan view of the main part showing a modification of the flow stopper. FIG. 3 is a perspective view of a conventional hybrid IC, and FIG. 4 is an enlarged plan view of the same essential parts. 2... Semiconductor pellet, 5... Mounting land, 9
...Conductive adhesive, 16...Wiring pattern, 17...
...Leader wire, 17a... Stopping portion, 18... Electrode bonding land (stitch land), 18
a...Tip.
Claims (1)
配線と、前記引出し配線の近傍に、先端部が搭載
ランドから離隔した電極ボンデイングランドとを
有する配線パターンを絶縁基板上に形成し、かつ
、上記搭載ランド上に導電接着材を介して半導体
ペレツトをマウントしたハイブリツドＩＣにおい
て、 上記引出し配線の上記電極ボンデイングランド
先端部より搭載ランドに近接した位置に、所定形
状の上記導電接着材の流れ止め部を形成したこと
を特徴とするハイブリツドＩＣ。[Claims for Utility Model Registration] A wiring pattern is formed on an insulating substrate, the wiring pattern having a lead-out wiring continuous to a mounting land for a semiconductor pellet, and an electrode bonding land whose tip end is spaced from the mounting land near the lead-out wiring. , and in a hybrid IC in which a semiconductor pellet is mounted on the mounting land via a conductive adhesive, the conductive adhesive having a predetermined shape is placed at a position closer to the mounting land than the tip of the electrode bonding land of the lead-out wiring. A hybrid IC characterized in that a flow stopper is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989075932U JPH0313752U (en) | 1989-06-27 | 1989-06-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989075932U JPH0313752U (en) | 1989-06-27 | 1989-06-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0313752U true JPH0313752U (en) | 1991-02-12 |
Family
ID=31616945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989075932U Pending JPH0313752U (en) | 1989-06-27 | 1989-06-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0313752U (en) |
-
1989
- 1989-06-27 JP JP1989075932U patent/JPH0313752U/ja active Pending