JPH0459960U - - Google Patents
Info
- Publication number
- JPH0459960U JPH0459960U JP10326190U JP10326190U JPH0459960U JP H0459960 U JPH0459960 U JP H0459960U JP 10326190 U JP10326190 U JP 10326190U JP 10326190 U JP10326190 U JP 10326190U JP H0459960 U JPH0459960 U JP H0459960U
- Authority
- JP
- Japan
- Prior art keywords
- substrate bias
- capacitor
- generation circuit
- drain
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims 4
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案に係る基板バイアス発生回路の
回路図、第２図は、本考案に係る基板バイアス発
生回路の基板バイアス電圧ＶＢＢ対電源電圧ＶＤ
Ｄ特性図、第３図は従来例に係る基板バイアス発
生回路の回路図、第４図は従来例に係る基板バイ
アス発生回路の基板バイアスＶＢＢ対電源電圧Ｖ
ＤＤ特性図である。
ＯＳＣ……発振器、Ｃ……容量、Ｍ１……第１
のＭＯＳトランジスタ、Ｍ２……第２のＭＯＳト
ランジスタ、Ｍ３，Ｍ４，Ｍ５……ＭＯＳトラン
ジスタ、ＶＤＤ……電源電圧、ＶＳＳ……接地電
圧、ＶＢＢ……基板バイアス電圧、ＣＬＰ……ク
ランプ回路、Ｖｔ１，Ｖｔ２，Ｖｔ３，Ｖｔ４，
Ｖｔ５……しきい値電圧。
FIG. 1 is a circuit diagram of a substrate bias generation circuit according to the present invention, and FIG. 2 is a circuit diagram of a substrate bias generation circuit according to the present invention versus substrate bias voltage VBB versus power supply voltage VD.
D characteristic diagram, FIG. 3 is a circuit diagram of a substrate bias generation circuit according to a conventional example, and FIG. 4 is a substrate bias VBB vs. power supply voltage V of a substrate bias generation circuit according to a conventional example.
It is a DD characteristic diagram. OSC...Oscillator, C...Capacity, M1 ...First
MOS transistor, M 2 ... second MOS transistor, M 3 , M 4 , M 5 ... MOS transistor, VDD ... power supply voltage, VSS ... ground voltage, VBB ... substrate bias voltage, CLP ... clamp circuit, Vt 1 , Vt 2 , Vt 3 , Vt 4 ,
Vt5 ...Threshold voltage.
Claims (1)
た容量Ｃと、 前記容量Ｃの他の一端がドレインおよびゲート
に接続され、ソースが接地電圧に接続された第１
のＭＯＳトランジタＭ１と、 前記容量Ｃの他の一端がソースに接続され、ド
レインとゲートが互いに接続され、該接続点から
基板バイアスＶＢＢが取り出された第２のＭＯＳ
トランジスタＭ２とを具備する基板バイアス発生
回路において、 前記容量Ｃの他の一端と接地電位ＶＳＳの間に
ソースとゲートとが接続された複数のＭＯＳトラ
ンジスタを縦列接続してなるクランプ回路ＣＬＰ
が設けられ、該クランプ回路ＣＬＰによつて基板
バイアスを一定にクランプしたことを特徴とする
基板バイアス発生回路。[Claims for Utility Model Registration] An oscillator OSC, a capacitor C to which the oscillation output of the oscillator OSC is connected, the other end of the capacitor C is connected to a drain and a gate, and a source is connected to a ground voltage. The first
MOS transistor M1 , the other end of the capacitor C is connected to the source, the drain and the gate are connected to each other, and the substrate bias VBB is taken out from the connection point.
A clamp circuit CLP comprising a plurality of cascade-connected MOS transistors whose sources and gates are connected between the other end of the capacitor C and the ground potential VSS in the substrate bias generation circuit comprising a transistor M2 .
1. A substrate bias generation circuit characterized in that the substrate bias is clamped to a constant value by the clamp circuit CLP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10326190U JPH0459960U (en) | 1990-09-28 | 1990-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10326190U JPH0459960U (en) | 1990-09-28 | 1990-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0459960U true JPH0459960U (en) | 1992-05-22 |
Family
ID=31848068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10326190U Pending JPH0459960U (en) | 1990-09-28 | 1990-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0459960U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914665A (en) * | 1982-07-16 | 1984-01-25 | Nec Corp | Semiconductor device |
-
1990
- 1990-09-28 JP JP10326190U patent/JPH0459960U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914665A (en) * | 1982-07-16 | 1984-01-25 | Nec Corp | Semiconductor device |
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