JPH0462084B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a computer bus system in which modules can be easily added.

<Prior Art> A bus system constituting a computer is constructed by combining various modules having functions such as a CPU, memory, basic input/output, and optional input/output via a common bus line. FIG. 2 shows the bus line configuration behind the module mounting section of such a computer. In Figure 2, M ₁ is the CPU
module, M ₂ is a memory module, M ₃ is an input/output module, M ₄ , M ₅ ... are other input/output modules, B ₁ , B ₂ , B ₃₁ , B ₃₂ , B ₃₃ , B ₃₄ are each This is a bus line that connects modules behind the modules.

FIG. 3 shows the front side of the module arrangement of these module mounting sections. As shown in FIG. 3, each module M ₁ , M ₂ . . . has connectors 1 ₁ , 1 ₂ .
The CPUs inserted into these connectors 1 ₁ , 1 ₂ ...
It is formed from printed circuit boards 2 ₁ , 2 _{2 .} . . which constitute memory and various input/output functional circuits. The printed circuit boards 2 ₃ , 2 ₄ ... of the input/output modules M ₃ , M ₄ ... have another connector 3 ₁ , on the side opposite to the connector.
Multi-core cables 4 ₁ , 4 ₂ . . . are led out through 3 ₂ . . . and connected to an external circuit (not shown).

In computer bus systems such as those shown in FIGS. 2 and 3, signals are input and output to and from the CPU using a common bus line in an interrupt data exchange system generally called a TSG chain system. In the daisy chain method, if an interrupt is applied from any input/output module of the computer bus system, for example, input/output module _M4 , the interrupt signal a is sent from the input/output module _M4 to the bus line _B2.
and input to CPU module _M1 .
The CPU module _M1 returns a response signal b via the bus line _B1 in response to the interrupt signal a, and checks which input/output module has issued the interrupt signal a. Bus line B ₁ runs from the input terminal I of each module to the interrupt control circuit L _o , and then to the output terminal O.
are connected to the input terminal I of the next module. In addition, each module's interrupt control circuit
L ₂ , L ₃ . . . consist of a direct connection line L ₂ in the case of the memory module M ₂ and interrupt control circuits L ₃ , L _{4 .} . . in the case of the input/output modules M ₃ , M ₄ . If the interrupt control circuits L ₃ , L ₄ ... do not issue an interrupt in response to the response signal b from the CPU, the interrupt control circuit passes the response signal b to other adjacent input/output modules, and if In response to this response signal b, the input/output module, in this example input/output module M ₄ , transmits the coded signal c specific to that module to the bus lines B ₃₁ , B _{32 .} , B ₃₃ , and B ₃₄ to the CPU module M ₁ to notify the interrupt of that input/output module.

In this way, in the daisy chain method, the response signal b from the CPU module M ₁ in response to the interrupt signal a is transmitted via the bus line B ₁ that connects each module and the input/output terminals I and O of each module. , if the bus line _B1 is interrupted due to an empty module on the way, the response signal b may be interrupted. For this reason, expansion modules must be installed within the module mounting range, as shown by the dotted line in Figure 2.
Modules must be added adjacent to each other from one side closer to the CPU module without leaving any empty space.

<Problems to be solved by the invention> As shown in Fig. 3, the front side of the bus system constituting the computer shown in Fig. 2 has input/output modules M ₃ ,
On the side opposite to the bus lines B _{1 ,} B ₂ ... of M 4 ..., multi-core cables 4 ₁ , _{4 2} ... that connect external circuits to input/output modules M ₃ , M 4 ... connect connectors 3 ₁ , 3 ₂ ... It is connected through the CPU module _M1 and routed to the end opposite to the CPU module M1. Therefore, these multi-core cables vibrate in front of many input/output modules. Therefore, when it is necessary to replace or add an input/output module, the multi-core cables overlap and it becomes necessary to replace the connectors and the like, making the work extremely complicated.

For example, in Figure 3, input/output module M ₄
If you are adding a new input/output module _M5 to the right of the
Since the multi-core cables 4 ₁ and 4 ₂ of M ₃ and M ₄ cross and block the front surface of the connector 1 ₅ for the input/output module M ₅ , the connectors 3 ₁ and 3 ₂ of these multi-core cables
The input/output module could not be added unless the multi-core cables 4 ₁ and 4 ₂ were removed and the connectors 3 ₁ and 3 ₂ were inserted after the module was added.

Therefore, when adding a new input/output module as an option, etc., it is desired to develop a computer bus system that allows the module to be easily added without having to connect or disconnect the input/output multi-core cable of the existing input/output module. ing.

To do this, it is possible to add modules by leaving an empty space in the center for mounting input/output modules, but how to connect bus line _B1 for interrupt response signal b in the daisy chain method to the empty space for mounting input/output modules? It is important to avoid interruptions.

For example, using the technology disclosed in Japanese Patent Application Laid-Open No. 60-5310, pins can be set up corresponding to input/output modules, and the pins can be shot with a switch or a shot bar in the space where the input/output module is mounted. It is possible, but when adding an input/output module, it becomes necessary to change the switch or remove the shoot bar to open between the pins, making the work cumbersome.Furthermore, there is a possibility of forgetting to change the switch and making a mistake between shooting and opening. A new problem arises.

The present invention has been made in view of the various drawbacks of the prior art.
When adding new modules as options, etc., it is now possible to easily add new modules without having to disconnect or connect the input/output multi-core cables of existing input/output modules, or without having to change switches. The purpose is to provide a new bus system for computers.

<Means for Solving the Problems> In a computer bus system according to the present invention that achieves the above object, in a bus system in which a computer module is mounted, an interrupt response signal bus line is connected to one end of the mounting section. CPU implemented in
The interlaced wiring part is connected directly to the input/output module mounted on the opposite end of the module, and the jump wiring part is connected directly to the input/output module mounted on the opposite end of the module. Adjacent wiring portions between input and output modules are wired so that output modules are sequentially added and mounted.

<Embodiment> An embodiment of a computer bus system according to the present invention will be described with reference to FIGS. 1 and 4.

FIG. 1 is a perspective view of the back of a computer module mounting section showing the bus configuration of a computer according to the present invention. In FIG. 1, a CPU module M ₁ , a memory module M ₂ , a memory module M ₂ ', etc. forming a computer main body are sequentially arranged from the right side in FIG. 1 within the module mounting range. However, the input/output modules M ₃ , M ₄ ... are arranged sequentially from the leftmost side of the module mounting area toward the center.
Bus line B ₂ common to these modules,
B ₃₁ , B ₃₂ , B ₃₃ , B ₃₄ etc. are wired after the module arrangement as in the conventional case. However, in the bus configuration of the present invention, the input/output modules are added sequentially from the left side of Fig. 1 so that the module mounting space for adding options etc. is left in the center. Bus line transmitting response signal b from module M ₁
B ₁ has an interlaced wiring section 5 and an adjacent wiring section 6, and the interlaced wiring section 5 connects directly from the rightmost CPU module M ₁ to the input I of the leftmost input/output module M ₃ . Then, the modules M ₄ , M ₅ on the right side are connected by the adjacent wiring section 6.
Input/output terminal I between to and next and input/output module,
It is connected to O. Therefore, when an interrupt is generated by an interrupt signal a from a certain input/output module, the interrupt response signal b is inputted from the CPU module _M1 to the input/output module _M3 at the opposite end.
The information is then transmitted to the next modules M ₄ , M ₅ , etc. closer to the CPU module M ₁ .

Therefore, the input/output modules to be mounted in the module mounting range are sequentially mounted from left to right in FIG. 1. On the other hand, memory modules M ₂ and M ₂ ' do not have input/output multi-core cables like input/output modules, so they do not get in the way when they are expanded, and even if memory modules are expanded, they can be expanded continuously. They are implemented from right to left, that is, from the side closest to the CPU module _M1 , because it is more accurate in terms of addresses and is more advantageous in terms of maintenance and operation. Therefore, an empty space is left in the center. Bus lines B ₁ , B ₂ , B ₃₁ , B ₃₂ , B ₃₃ , B ₃₄
The configuration of one embodiment is as shown in FIG. 1, where the module is connected behind the connector that mounts the module.
In particular, bus line B ₁ runs from CPU module M ₁ to leftmost input/output module M ₃ . Therefore, in the case of the present invention, when adding modules, M ₃ , M ₄ , etc. are mounted from the left end side. Therefore, in the daisy chain system, the response signal b corresponding to the interrupt signal a sent to the bus line _B2 can be used to check the input/output modules one after another via the bus line _B1 , and the input/output modules in FIG. The module is mounted from the left end, leaving an empty space in the center, so the multi-core cable led out from the front of the previously mounted input/output module does not get in the way when mounting a new module. Unlike the conventional case, there is no need to remove the existing multi-core cable from the connector, making it extremely easy to add modules.

The ease of adding modules will be further explained with reference to FIG. 4. FIG. 4 shows the entire state of the bus system in FIG. _1. In _FIG .
M ₂ ′ is mounted in order, input/output modules M ₃ , M ₄ , M ₅ are mounted in order from the right end side, and uninstalled M ₆ ,
A space for mounting an input/output module for _M7 ... is left in the center. The input/output multi-core cables 4 ₁ , 4 ₂ , 4 ₃ of the installed input/output modules are CPU module M ₁
It is routed to the right side, which is the opposite side. Therefore,
When adding a new input/output module M ₆ to the left of input/output module M ₅ , input/output module M ₆
The front surface of the connector ₁₆ is open, and the input/output multicore cables 4 ₁ , 4 ₂ , 4 ₃ of the existing input/output modules M ₃ , M ₄ , M ₅ do not get in the way at all.

<Effects of the Invention> According to the computer bus system according to the present invention,
In the bus line wiring within the module mounting area, the bus line for interrupt response signals is routed in such a way that an input/output module mounting space is left in the center so that modules can be added. The multi-core cable for connecting the module to the external circuit does not get in the way when adding modules, and it is now extremely easy to add modules by simply mounting them one after the other from the end. Further, since there is no need to open or shoot between the pins using a switch or a shot bar, there is no troublesome switching work and no errors such as forgetting to switch occur. Furthermore, memory modules can be sequentially mounted from the CPU module side.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a computer bus system according to the present invention, FIG. 2 is a perspective view showing a conventional computer bus system, FIG. 3 is a perspective view showing the front side of the computer shown in FIG. FIG. 4 is a perspective view showing the front side of the device shown in FIG. 1 for explaining the effects of the present invention. In the drawing, M ₁ is a CPU module, M ₂ , M ₂ ' are memory modules, M ₃ , M ₄ , M ₅ ... are input/output modules, B ₁ , B ₂ , B ₃₁ , B ₃₂ , B ₃₃ , B ₃₄ is a bus line, L ₁ , L ₂ ... are interrupt control circuits, 1 ₁ , 1 ₂ ... are connectors, 2 ₁ , 2 ₂ ... are printed circuit boards, 3 ₁ , 3 ₂
... are connectors, 4 ₁ , 4 ₂ ... are multi-core cables, 5 is an interlaced wiring portion, and 6 is an adjacent wiring portion.

Claims (1)

[Claims] 1. In a bus system in which computer modules are mounted, the interrupt response signal bus line is directly connected from the CPU module mounted at one end of the mounting section to the input/output module mounted at the opposite end. The connected jump wiring part,
Adjacent wiring portions between the input/output modules are wired so that the input/output modules are sequentially added and mounted from the end side opposite to one end side where the CPU module and memory module are mounted. Features a computer bus system.