JPH0464224A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To replace Si completely with W at high speed by a method wherein the surface of an Si layer is exposed selectively, the Si layer is brought to a porous state, the Si layer brought to the porous state is brought into contact with the vapor of the halide of a metal, a chemical reaction is accelerated, and the Si layer is replaced with a metallic layer. CONSTITUTION:A window is bored at the central section of a partition wall 24, and an Si substrate 22 is stuck so as to close the window. A solution obtained by adding alcohol to 50% diluted hydrofluoric acid is used as an electrolyte 2l on the substrate surface side, and an electrolytic solution is employed as an electrolyte 21' on the rear side. When voltage is applied, ion currents flow, and Si eluates from the Si substrate. The speed of travel of atoms and molecules in the direction vertical to a substrate surface is increased largely. Accordingly, when W replacement treatment is executed while using a Si layer brought to a porous state as an object, the speed of supply of WF6 vapor and the speed of discharge of SiF4 as a reaction product are accelerated, thus replacing all Si in a connecting hole with W in a comparatively short time.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to the formation of connection wiring or internal wiring of a semiconductor integrated circuit device, and aims to provide a processing method for forming metal wiring of sufficient thickness in a finer space. a step of selectively depositing a Si layer on the surface of the semiconductor substrate or a step of selectively exposing the Si surface of the semiconductor substrate or the surface of the Si layer deposited on the semiconductor substrate; immersing it in an electrolytic solution and applying an electric field to make the Si layer in contact with the electrolytic solution porous; and bringing the porous Si layer into contact with metal halide vapor; A method for manufacturing a semiconductor device is characterized in that it includes a step of proceeding with a Hokugaku reaction to replace the Si layer with the metal layer.

[Industrial application field]

The present invention relates to the formation of internal wiring in a semiconductor integrated circuit device (hereinafter abbreviated as IC), and in particular, the present invention relates to the formation of internal wiring in a semiconductor integrated circuit device (hereinafter abbreviated as IC), and in particular, by filling holes or grooves drilled in an insulating material layer with a metal material to form connection wiring or internal wiring. It is related to the processing method used to form .

As ICs become more highly integrated and element patterns become finer, internal wiring patterns also become finer, and the opening areas of contact holes for connecting internal wiring to element areas and through-holes for connecting between the eyebrows of multilayer wiring also become extremely small. It is becoming more and more popular. On the other hand, since the thickness of the glabellar insulating layer has not been reduced commensurately, these contact holes have a large aspect ratio. Hereinafter, in this specification, through holes and contact holes will be collectively referred to as connection holes.

When the opening area of the connection hole decreases and the aspect ratio increases,
In order to reliably connect the wiring via the connection hole, it is necessary to provide a separate process of filling the connection hole with a conductor.

That is, a connection hole is made in the glabella insulating layer and the connection hole is filled with a conductive material to achieve a shape in which the upper end of the connection wiring is exposed on the flat outermost surface of the substrate, and then the upper layer wiring is formed.

To fill a contact hole with a large aspect ratio with a conductive material, the conductive material layer is deposited using a process that provides good coverage, and the unnecessary portion is removed by etchback, or the deposition progresses only on a specific material surface. This is done by selectively growing the material within the connection hole depending on the treatment method.

Regardless of which method is used, good coverage is required to deposit the conductive material inside the connection hole, so a deposition method with poor coverage, such as sputtering, cannot be used.
A method such as low-pressure CVD must be used, and therefore it is difficult to use a conventional metal material such as sputtered Al to fill the connection hole.

On the other hand, poly S1, which has good coverage and can be deposited by a method such as low-pressure CVD, has a resistivity that does not decrease as much as a metal layer even if the amount of impurity doping is maximized, and the connection resistance is sufficiently low. The problem is that it cannot be done.

[Conventional technology]

In order to deal with this problem, a processing method for selectively growing a tungsten (W) layer has been proposed, and various improvements have been made toward practical use. This is tungsten hexafluoride (W
The vapor of a W halide such as
The basic principle is that when brought into contact with the i surface, WF6 is reduced according to the following equation (1), and W is precipitated.

WFb + 3/2Si→ W↓+3/2SiF4↑ −・−1−−・+(1) As described above, if precipitation proceeds in the form of reduction of W by Si, Si will eventually be replaced by W. It becomes a shape. St may be polycrystalline or single-crystalline, but since polycrystalline has a higher diffusion rate, the substitution rate is relatively high.

Further, WF also precipitates by thermal decomposition, but it is easier to precipitate on the surface of a conductor than on the surface of an insulator, and it can be selectively grown by appropriately setting processing conditions. In that case as well, it is usual to first precipitate W on the Si layer and then continue the deposition.

Furthermore, similar processing is possible using halides of metals other than W, such as molybdenum (MO), chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V),
Deposition of metal layers with halides of zirconium (ZrL aluminum (A1)) is possible.

[Problems to be Solved by the Invention] A connection hole with a minute opening diameter provided in a glabellar insulating film having a thickness of about 100 to 100 mm has a large aspect ratio.

Filling this with poly-Si is possible by a well-known method that is a combination of low pressure CVD deposition and etch banks, but the small opening diameter means that the WF, 4Q supply rate is small. In other words, if all Si in the connection hole is replaced with W, the processing time will be long. Furthermore, if the replacement with W is partially stopped in order to shorten the processing time, the intended purpose of reducing connection resistance will not be achieved.

An object of the present invention is to provide a processing method that can replace the 31 layer with a W layer in a shorter time, thereby making it possible to form an IC with a higher degree of integration.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of selectively depositing a Si layer on the surface of a semiconductor substrate, or a step of selectively depositing a Si layer on the surface of the semiconductor substrate or depositing a Si layer on the semiconductor substrate. selectively exposing the layer surface; immersing the semiconductor substrate in an electrolyte and applying an electric field to make the Si layer in contact with the electrolyte porous; The method includes a step of bringing the Si layer into contact with vapor of a metal halide to allow a chemical reaction to proceed and replacing the Si layer with the metal layer.

[Function] It has been known for a long time to electrolytically treat Si to make it porous, and various uses have been proposed, such as use as an auxiliary means for promoting selective oxidation.

Regarding the porous treatment of Si, for example, G, Bomch
il, Ni, BarLa, J, EIectrochem.
, Soc, + 1301611 (1983) or Y, Kato, T, Ito, A, HirakiJapa
nese J, Appl, Phys, 27. Li2O
2 (1988).

The most basic method of this electrolytic treatment is to apply electricity in a hydrofluoric acid-based electrolytic solution to a Si substrate as a positive electrode and a platinum (Pt) plate opposite to this as a negative electrode to elute Si. As shown in FIG. 3, the electrolytic treatment used is performed by partitioning the electrolytic cell 20 with partition walls 24, providing Ptt electrodes 23 on both sides thereof, and applying a voltage between both the PT electrodes.

A window is opened in the center of the partition wall 24, and the 51 substrate 22 is attached so as to close this window. The electrolyte 21 on the front side of the Si substrate is usually 50% dilute hydrofluoric acid with alcohol added as a buffer, and the electrolyte 21' on the back side is an electrolyte solution such as dilute sulfuric acid or potassium sulfate solution. be.

When a voltage is applied to the electrolytic treatment apparatus having such a configuration as shown in the figure, an ionic current flows and Si is eluted from the Si substrate. The corrosion holes created by this treatment are mainly small in diameter and extend vertically toward the inside of the substrate.
Significantly increases the speed of movement of atoms and molecules in the direction perpendicular to the substrate surface.

When W substitution treatment is applied to a porous material as described above, the supply rate of WF61 gas and the reaction product Si
Since the discharge rate of F4 is high, the reaction between Si and WF proceeds rapidly, and all the Si in the connection hole is replaced with W within a relatively short time. The reason why the electrolytic treatment is performed with the partition wall provided is to prevent Na' ions from being taken into the Si substrate.

(Example) FIG. 4 is a diagram showing an electrolytic treatment apparatus used when carrying out the present invention. This is a concrete embodiment of the basic configuration shown in FIG.
The back side of the substrate is in contact with the second electrolyte. The first electrolytic solution on the surface side of the substrate is a mixture of 50% dilute hydrofluoric acid and alcohol.

Here, the electrolytic treatment is carried out at a current density of several mA to several tens of mA/cm2, but this electrolytic treatment belongs to a known technique, and the treatment conditions may be appropriately selected and carried out.

FIG. 1 is a schematic cross-sectional view showing the steps of a first embodiment of the present invention, and this embodiment will be described below with reference to the drawings. In this embodiment, contact wiring is formed in an element region formed on a Si substrate.

In the same figure (a), the surface of the Si substrate 10 is coated with SiO2
After forming a connection hole 13 in a portion of the element region 11 where a contact is to be formed, TiN is coated as a barrier film in the hole.
This shows a state in which the film 14 is formed by a CVD method.

This barrier film can be deposited on the entire surface as shown in the figure, and unnecessary parts can be removed, or it can be deposited selectively only on the Si surface inside the connection hole by adjusting the processing conditions during formation. Good too. Further, since this film is provided to prevent the element region from becoming porous in the subsequent electrolytic treatment, it is not necessary when forming an interlayer connection portion on the lower layer wiring.

To form a TiN film, titanium tetrachloride (T i Cl 4 ) was added at 10 cm/win and ammonia (NH was added at 100 cm3/min to H2100 cm3/min.
This is carried out by supplying a raw material gas mixed with min. In addition, as a barrier film, Cr,
Solicide of Ti, W, Co, Mo, or Ta may be used, or it may be formed by sbanking if a sufficient film thickness is obtained.

A poly-Si layer is deposited on the entire surface by CVD and etched back to fill the connection hole with poly 5i15, as shown in FIG. 1(b). Deposition of poly-Si by CVD may be performed by a known method, but monosilane (SiH4), disilane (SizH-), trisilane (SizHa), halogenated silane (for example, 5iHF31), etc. are used as raw materials, and the temperature is about 600 to 900'C. A common method is to thermally decompose Si by bringing it into contact with a heated substrate. According to this method, by setting the substrate temperature low, amorphous Si
can be deposited and when carrying out the present invention,
The poly-Si formed here may be amorphous S1. Furthermore, it is desirable to dope impurities into this poly-Si or amorphous S1 using B, H, or PH3 to make it low in resistance.

A metal film 16 is deposited on the entire surface of the substrate. This metal film is, for example, a W film, and because the electrolyte in which the substrate is immersed in a subsequent step is a hydrofluoric acid-based electrolyte, it serves as a mask to prevent the 5iOz from dissolving. A window is opened in the W film to match the poly-Si in the connection hole, and the poly-Si surface is exposed. At this time, the opening area of the window is made slightly smaller to ensure that the 5iOz layer is masked.

If the W film is connected to poly-Si, there is also the effect that porosity progresses in the subsequent electrolytic treatment without being affected by the pn junction formed in the substrate. The formation of the W film here also utilizes the precipitation of W from WF, but W is deposited by thermal decomposition to form a film. Barrier film 1
If the SiOz coating according to No. 4 is sufficient, the step of coating with the W film may be omitted.

The substrate No. 31 that has undergone the above treatment is electrolytically treated using the electrolytic treatment apparatus shown in FIG. 4 to make the holes in the connection holes porous. This state is shown in FIG. 1(C), where Si is made porous at 15°.

Thereafter, the W film covering the surface of the substrate is removed by etching.

The substrate was then heated to 500'C and WF steam was added to 50'C.
It is supplied to the substrate surface at a speed of m'/ll1n. pressure is 1
~760 Torr, and here it is set to 50 Torr.

In this treatment, the reaction of formula (1) proceeds, and the poly-Si in the connection hole is replaced with W, but since the poly-Si is porous, the exchange with W takes place quickly. The conversion of poly-Si having a large aspect ratio to W can also be completed in a relatively short time. As shown in FIG. 1(d), W17 is formed which is substituted with poU S i.

In this example, Si was replaced with W, but
As already mentioned, MOlCr, Ti, Ta, V, Zr,
It is also possible to substitute metals such as Cu, Al, etc. for Si. MoFb for Mo, TiCj for Ti! ,
Halides such as are used.

The above explanation is based on the case where the present invention is used to fill contact holes, but in order to increase the number of layers of internal wiring in highly integrated ICs, the surface It is required to planarize the wiring layer, and the present invention can also be used to form this type of planarized wiring layer.

Next, the wiring pattern is created using the present invention! ! , an example in which it is formed by being embedded in a curbstone will be described.

FIGS. 2(a) to 2(d) are schematic diagrams showing the steps of a second embodiment of the present invention. Hereinafter, reference will be made to the drawings.

As shown in the same figure (al), an interlayer insulating film 12 of SiO□ is provided on the Sig board 10, and a groove 18 corresponding to the wiring pattern is formed.If the internal wiring formed here is the lowest layer wiring, then Below the insulator 1112 is a substrate on which elements are formed, and in the case of forming an upper layer wiring of a multilayer wiring, an insulating material layer in which a lower layer wiring is embedded exists under the interlayer insulating layer 22.

When forming the groove 18 by etching, if the lower layer is made of the same material as the material to be drilled, there is a risk that the lower layer will be etched. It is better to provide a barrier to prevent excessive etching.

Next, a metal barrier 11114 is applied to the entire surface, and polyS
iF! 15 is deposited and formed. This barrier film is, for example, a W film, and is deposited by a low pressure CVD method using WF. Poly-Si was deposited by low pressure CV as in the first embodiment.
D method is used to deposit excessively to the extent that the unevenness of the surface becomes unclear. This situation is shown in FIG. 4(b).

Furthermore, anisotropic etching such as RIB is performed to leave poly-Si only in the grooves. Wl! A porous treatment is performed in the same manner as in the first embodiment while the pores remain on the entire surface. The processing device is also the same as that shown in FIG.

This situation is shown in Figure FC), where 15'' is the porous poly S1. Here again, the poly S1 may be amorphous Si.

After completing the above treatment, the W film on the surface is removed, and WF and steam are supplied to the surface while keeping the substrate at a high temperature, and the porous poly-Si is replaced with W, as shown in Figure 2(d). A W interconnection 17 embedded in Si◯ 21i is formed as shown in FIG. The processing conditions for converting Si into W using W F b are the same as in the first embodiment.

[Effects of the Invention] In both the first and second embodiments described above, after poly-Si is made porous, a process of converting it into W is performed.

Figure 3 shows poly S as deposited.
Fig. 3 shows the change in the thickness of the W layer with elapsed time when porous poly-Si was treated under the same conditions. As is clear from the figure, not only does the W substitution rate become more than 2.5 times faster by making it porous, but if it is not made porous, the thickness of the film substituted by W becomes saturated, and the thickness of the poly-Si layer increases. If the length exceeds 10Or+a+, all of it is
However, it has been shown that Si made porous as in the present invention progresses without becoming saturated.

In this way, in the present invention, the W ratio treatment progresses at high speed and deep into the layer, so even in connection holes with small opening diameters and large aspect ratios, the poly-Si inside the holes can be completely and quickly removed. can be replaced with W.

According to the formation of the wiring pattern described as the second embodiment, it is also possible to form internal wiring of Cu. It is somewhat difficult to form a film on Cu compared to other metal materials, and since no suitable selective etching method is known, it is also difficult to form wiring patterns.

According to the method of the present invention, selective etching of the Cu film is not required, so that internal Cu wiring can be easily formed.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional diagram showing the steps of the first embodiment, FIG. 2 is a schematic diagram showing the steps of the second embodiment, and FIG. 3 is a schematic diagram showing the basic porosity processing apparatus. FIG. 4 is a diagram showing the porous processing apparatus used in the present invention, and FIG. 5 is a diagram showing the processing speed of the present invention and the conventional technology. In the figure, 10 is a Si substrate, 11 is an element area. , 12 is an interlayer insulating film, 13 is a connection hole, 14 is a barrier film, 15 is poly-Si, 15' is porous Si, 16 is a metal film, 17 is W, 18 is a groove, 20 is an electrolytic cell, 21 is 22 is a Si substrate, 23 is a Pt electrode, and 24 is a partition wall. 15 Poly S 15 Poly Si 7W Schematic cross-sectional diagram showing the process of the first example Figure 1 7W Schematic diagram showing the process of the second example Figure 2 21 Electrolyte tHFROII+ 21° Electrolyte (weak electrolyte ) Schematic diagram showing the basic porous treatment device Diagram showing the porous treatment device used in the present invention Processing time (sec) Diagram showing the processing speed of the present invention and the conventional technology

Claims (7)

[Claims] (1) A step of selectively depositing a silicon (Si) layer on the surface of the semiconductor substrate or a step of selectively exposing the Si surface of the semiconductor substrate or the surface of the Si layer deposited on the semiconductor substrate; By immersing the semiconductor substrate in an electrolytic solution and applying an electric field,
a step of making the Si layer in contact with the electrolytic solution porous; and bringing the porous Si layer into contact with metal halide vapor to advance a chemical reaction to transform the Si layer into the metal layer. 1. A method of manufacturing a semiconductor device, comprising the step of substituting with. (2) In the method for manufacturing a semiconductor device according to claim 1, the S
A method for manufacturing a semiconductor device, wherein i is polycrystalline, amorphous, or single crystalline. (3) The method of manufacturing a semiconductor device according to any one of claims 1 to 2, wherein the conductivity type of the Si is p-type or n-type. (4) In the method for manufacturing a semiconductor device according to claims 1 and 2, the metal to be replaced with Si is tungsten (W),
Molybdenum (Mo), chromium (Cr), titanium (Ti)
, tantalum (Ta), vanadium (V), zirconium (Zr), copper (Cu), or aluminum (Al). (5) The metal layer formed by the step characterizing the method for manufacturing a semiconductor device according to any one of claims 1 to 4 fills a contact hole for forming a contact electrode in an element region of the semiconductor substrate. A semiconductor device characterized by the following. (6) The metal layer formed by the step characterizing the method for manufacturing a semiconductor device according to any one of claims 1 to 4 fills a through hole for forming a connection wiring to an internal wiring on the semiconductor substrate. A semiconductor device characterized by: (7) A semiconductor device, wherein the metal layer formed by the steps characterizing the semiconductor device manufacturing method according to any one of claims 1 to 4 is an internal wiring on the semiconductor substrate.