JPH0464263A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce clock skew by preparing for clock distribution as a slice pattern and selecting a clock distribution cell in conformity with the number of load. CONSTITUTION:A master chip 1 is provided with a plurality of cells comprising transistors to embody predriver cells 4 for the portion of several phases and main driver cells 5. A slice cell is prepared as a macrocell library in advance where an Al wiring is formed on the slice cell in order to interconnect the predriver and main driver cell mounted on the master chip 1 and supply a clock to an internal gate. This construction allows the clock driver to select a number of sequence and drive the circuit collectively, thereby reducing the skews for a cock signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly provides a gate array LSI of a spread type, which reduces clock skew and realizes high-speed LSI. It is.

[Conventional technology]

FIG. 6 is a plan view of a conventional semiconductor integrated circuit device disclosed in Japanese Unexamined Patent Publication No. 63-108748. In the figure, (1) is the gate array LSI, (2) is the peripheral area, (3) is the internal area, (4) is the transistor row, (5) is the
) is the wiring area, (6) is the clock driver circuit, (7)
indicates clock wiring.Clock driver circuits (6) are installed on the extension line of transistor rows (4) at least once for all transistor rows.
At the same time, a clock wiring (7) is provided in the wiring area (5) parallel to each transistor column (4), and the output terminal of the clock driver circuit (6) and the clock wiring (7) are connected. The length of each clock wiring line is made equal to ensure the synchronicity of the clock signals.

[Problem to be solved by the invention]

Conventional semiconductor integrated circuit devices are configured as described above, but since all transistor rows are provided with clock driver circuits, there is a problem in that the area penalty is large. There is no mention of any means for solving the case where the phase is used, and if the conventional technology is used as is, it will be necessary to provide clock driver circuits for multiple phases, and the area penalty will be several times the original size, making it unsuitable for practical use. The problem was that there was no. However, in the gate array of the spread type, if at least one clock driver circuit is provided in the internal transistor row in advance, the number of circuits becomes enormous and the problem of area penalty becomes noticeable0. The invention was made to solve the above-mentioned problems.Whether the number of phases of the clock to be realized is one or multiple, it is compatible with the number of phases and the number of loads connected to each clock. An object of the present invention is to obtain a semiconductor integrated circuit device that can reduce clock skew by selecting a clock distribution cell that has the following characteristics.

[Means to solve the problem]

A semiconductor integrated circuit device according to the present invention includes a gate array LS
In addition to embedding the I clock driver circuit in the master chip for multiple phase molecules, the clock distribution cells for one phase and multiple phases are sliced and turned (hereinafter referred to as a library).
A clock distribution cell suitable for the number of clock phases and number of fan-outs is selected according to the user's circuit, and then placed and routed.

[Effect]

In the gate array LSI of the present invention, low-skew clock distribution of one phase or multiple phases can be realized without using a special wiring program.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the master chip of the gate array LSI, (2) is the buffer area around the LSI, and (3) is the master chip of the gate array LSI.
is an internal gate region where an internal gate is arranged, (4) is a pre-driver cell arranged in the internal gate region (2), and (5) is a main driver cell arranged in the internal gate region (2).

The second cell is an enlarged view of the gate 1 chip in the internal gate area (3) of FIG. 1, with PMO 8 and NMO 8 arranged above and below, respectively.

FIG. 3 is a diagram showing a slice cell for realizing a two-phase clock, in which the fixed cell shows the first clock A and the cell shown in FIG. B1 shows the cell for realizing the second clock B.

FIG. 4 is a plan view of a gate array showing a specific arrangement according to this embodiment, and shows a case in which two-phase clock distribution is realized. In the figure (4A), clock A1 (4B) has clock B. main driver (5A) and (5A), respectively.
B) internal ring-shaped clock signal wiring (6A),
(6B), the structure is such that it is distributed to internal gates.

Figure 5 is a detailed enlarged view of one chip in the internal gate area (3), where (6z) is a clock signal line made of second layer metal that is thicker than the normal signal line following the output of the clock driver, and (6X) is a A clock signal line made of first layer metal connected to the clock signal line (6z) via a through hole, (
6y) is a clock signal line made of second layer metal connected to the clock signal line (6x) via a through hole, (7)
is a clock branch line formed by the first layer metal wiring connected to the clock signal lines (6y) and (6z) via through holes,
(8) is a clock signal line formed by the second layer metal wiring connected from the clock branch line (7) via a through hole;
(a) is a sequential circuit such as a flip 70 tube, (9b) is a combinational circuit, and GO is a second eyebrow power supply wiring made of a second layer metal that supplies power to the areas of internal cell circuits (9a) and (9b). Clock signal lines (6x) and (6y) (r) form a ring-shaped wiring, and the clock signal line (8) connects the clock branch line (7) and the input terminal of the sequential circuit (9a).

Further, clock signals @(6x) and (6y), a clock signal line (6z), a clock branch line (7), and a clock signal line (82) constitute clock signal wiring.

Next, the operation will be explained. As shown in Fig. 1, a master chip (1) is prepared in advance, which is equipped with a plurality of cells each consisting of a plurality of cells made up of useless transistors to realize a pre-driver cell (4) for a plurality of phases and a main driver cell (5). put. As shown in Figure 3 (when realizing a two-phase clock), the pre-driver mounted on the master chip (1), the main driver (cells (4: l, (5)) are connected and the internal gate ( 4) A for supplying the clock to
A slice cell in which four wirings are formed is created in advance as a macro cell library as shown in Table 1. In Table 1, there is a limit to the driving ability of the pre-driver, main driver cells (4) and (5) placed on the master chip (1), and the maximum number of fanouts that can be operated within the chip is limited. Cell type 1 shown as ``S'' is a cell for one-phase clock, type 2.3 is a cell for two-phase or three-phase clock, and type 4 is a cell for four-phase clock.

Table 1 Cell library example Table 2 Clock cell combination example Type 1 FO = 20001 phase 2 phase Type 4 Type 3 x 2 Type 3 + Type 4 Type 4 x 2 FO = 500 1 phase FO = 10002 phase FO = 10001 phase + FO = 5001 Phase FO=500
2-phase (FO=20 (for D) “”” 12 (
FO=15CD) 0D3"", CD2A,
CD2kl 3 6(F”0
= for ICffl) Type 4X3 FO=500 3 phase 4
Phase type 4X4 1 FO=500
Also, as Table 2 shows examples of combinations of the clock cells in Table 1, clocks of 1 to 4 phases can be realized on a chip by overlapping each macro cell.

Next, the wiring method and operation of the internal cell region according to the embodiment of the present invention will be explained. In the semiconductor integrated circuit device shown in the fifth example, the clock signal lines (67) and (6Z) are wired in advance in the same manner as the second layer power supply wiring q0, and the power supply line q0 is wired in advance. Since the area where the clock signal lines (6y) and (6z) are wired is treated as an internal gate and second layer power wiring prohibited area in the wiring program, it does not affect the wiring of normal signal lines by the wiring program. Also, the clock signal! (6K) wiring,
A wiring area is secured in advance inscribed in the input/output buffer area (2) and treated as an area where internal cell placement is prohibited and signal wiring by first layer metal is prohibited, so normal signal line wiring using a wiring program is not possible. It does not affect. Clock branch line (7)
It is necessary to make the clock signal lines (67) thicker than normal signal lines in order to suppress skew, but the number of clock signal lines (67), (
6Z) can be easily done using current commercially available layout tools. Furthermore, the connection between the clock signal line (8) and the sequential circuit (9a) can be easily made using a commercially available rape plate tool.

In this way, a large number of sequential circuits (9a) can be collectively driven by a clock driver without a special program for clock signal wiring, so that it is possible to reduce the skew of clock signals. That is, since each clock signal line is arranged in a mesh shape, the resistance from the clock driver to the order circuit 11 is reduced, and the skew of the clock signal is reduced.

〔Effect of the invention〕

As described above, according to the present invention, by embedding a clock drive circuit in a master chip for multiple phase molecules and switching the number of pre-driver and main driver circuits according to the driving force, clocks for one phase and multiple phases can be generated. Since slice cells for distribution are prepared as a library, it is possible to distribute clocks according to the number of clock phases and the number of fanouts.

[Brief explanation of the drawing]

FIG. 1 shows a gate array LSI that is an embodiment of the present invention.
FIG. 2 is an enlarged view of one chip of the internal gate region of the X section in FIG. 1, FIG. 3 (4), CB
) is an enlarged view of the clock person and clock B of the pre-driver cell (4) in Figure 1, and Figure 4 is an enlarged view of the gate array LS in Figure 1.
A concrete plan view when two-phase lock distribution is performed on I,
Figure 5 is an enlarged view of the internal gate area of Figure 4 for one chip;
FIG. 6 is a plan view showing the internal arrangement structure of a conventional gate array LSI, in which (1) is a master chip, (2) is an engineering/○ buffer 7 area, (3) is an internal gate area, 4) is a pre-driver cell, (5), (5A), (5B) are main driver cells, (4 people) are clock A, (4B) is clock B, (6A). (6B) Beam 07 signal wiring, (5z) ~ (6z),
(8) is a clock signal line, (7) is a clock signal branch line, (9a) is a sequential circuit, (9b) is a combinational circuit, α
O indicates the second layer power supply wiring. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A master chip is equipped with a plurality of pre-driver transistor cells that receive a clock signal and a plurality of clock driver transistor cells that receive the output of the pre-driver transistor and drive internal cells. Semiconductor integrated circuit device.