JPH0465409B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microcomputer device, and in particular, a microcomputer device that includes a CPU and a data memory (RAM) for storing data processed by the CPU on the same semiconductor substrate. This invention relates to a microcomputer device in which the contents of this data memory can be monitored externally.

[Conventional technology]

When debugging a microcomputer device that has a CPU and a data memory (RAM) for storing data processed by this CPU on the same semiconductor substrate, for example, if the contents of a specific address of this data memory are It is often necessary to monitor which steps in a program have changed.

In such cases, the conventional method is to run the program to be debugged in one step, and then
The method used is to read and check the contents of RAM.

[Problem that the invention seeks to solve]

However, in this method, when reading data from the data memory, the program to be debugged is stopped, so real-time processing is impossible.

Recently, devices that perform real-time control using microcomputers have become widely used, but when debugging such devices during the development stage, it is difficult to debug them because real-time operation cannot be performed using the conventional methods described above. is often very difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microcomputer device which eliminates the above-mentioned drawbacks of the prior art and allows real-time operation while monitoring the contents of a specific address in a data memory.

[Means for solving problems]

The device of the present invention includes at least a RAM and a CPU on the same semiconductor substrate, and stores data processed by the CPU in the RAM via a data bus, or reads out the contents of the RAM and processes it in the CPU. In microcomputer equipment,
a control signal line for transmitting a machine cycle control signal indicating that the data bus is in an unused machine cycle state output by the CPU;
a monitor address input line that inputs a monitor address that specifies the address of the RAM regardless of an instruction executed by the CPU; and an address selection circuit that selects the monitor address input line as the address input of the RAM based on the machine cycle control signal. , and a storage circuit for storing and outputting to the outside the contents of the RAM specified by the monitor address and output to the data bus by the machine cycle control signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment includes a CPU 1, a data memory 2, a multiplexer 3, a data register 4, and a program memory 5.

This embodiment shows an example in which the present invention is applied to an evaluation chip of a single-chip microcomputer, and the part surrounded by the dotted line in FIG. Reference number 10) is a chip for evaluation of a single-chip microcomputer made on the same semiconductor substrate, and data memory 2 is
It consists of a RAM provided on the same semiconductor substrate as the CPU 1.

Program memory 5 is masked in the final product single-chip microcomputer.
Although it should be provided on the same semiconductor substrate in a single-chip microcomputer by ROM etc., in this evaluation chip 10, a separately prepared test control processor (supervisor, not shown) is used for management. Debugging is facilitated by using an external RAM under which the contents can be freely rewritten.

Now, the operation of this embodiment is as follows.

CPU 1 specifies the address of program memory 5 via program address bus 1500,
The instruction to be executed from this designated address is read into the CPU 1 via the program data bus 5100, and the instruction is decoded and executed. Data necessary for executing the instruction is stored in the data memory 2, and the CPU 1 outputs the data address specified by the instruction via the RAM address bus 1300 in order to execute the instruction.

Now, in the normal case, multiplexer 3 is
A logic "0" control signal supplied from the CPU 1 via the control line 1000 selects the side of the RAM address bus 1300 and supplies this as an addressing signal for the data memory 2. As a result, the CPU 1 reads the data at the address specified by the instruction from the data memory 2 via the data bus 2100, performs the necessary processing, and returns the data to the storage address in the data memory 2 specified by the instruction. Can be stored.

In this way, as long as the multiplexer 3 selects the RAM address bus 1300, the present embodiment operates in exactly the same manner as the conventional example, decoding and executing each instruction of the program stored in the program memory 5 one after another. do.

Now, among the instructions executed by CPU 1, there are instructions such as jump instructions that include machine cycles in which CPU 1 does not use the data bus 2100 at all (in jump instructions, the jump destination address is specified). The data to be
Generally, since this instruction is included as an operand of this jump instruction, this instruction is processed without reading data from data memory 2, resulting in a machine cycle in which data bus 2100 is not used. ) In this way, in a machine cycle in which the data bus 2100 is not used, the CPU 1 outputs a logic "1" to the control line 1000 as information indicating that the machine cycle does not use the data bus. This information indicating a machine cycle in which the data bus is not used is supplied to the multiplexer 3 as a selection control signal, a data memory 2 read designation signal, and a register 4 latch signal via line 1000, and is also used externally. It is also output to the outside of the chip 10 as a signal.

Now, the multiplexer 3 supplied with a logic "1" via the line 1000 selects the side of the monitor address input line 3000 and uses the monitor addressing input supplied via this as the addressing signal for the data memory 2. supply

As a result, the monitor address input line 3000
The contents of the address of the data memory 2 specified via the data bus 2100 are read out via the data bus 2100,
Latched into data register 4. Therefore, by supplying a signal specifying the address to be read in the data memory 2 from the outside via the monitor address input line 3000, each time a machine cycle in which the CPU 1 does not use the data bus 2100 appears, The data at the designated address in data memory 2 is read out to data address register 4 and latched. Therefore, by referring to the signal on the control line 1000 outputted to the outside and reading the contents of the data register 4, it is possible to check whether the contents of the specified address in the data memory 2 have changed.

This check is performed using the test control processor (supervisor) mentioned above, and when a change is detected, the program being debugged is run.
By stopping the program and knowing the instruction being executed at this time, it becomes possible to analyze within which range of the program being executed this change occurred.

Moreover, the contents of the specified address in the data memory 2 can be read out without affecting the operation of the program executed by the CPU 1, thereby making it possible to read the contents of the specified address in the data memory 2 without affecting the operation of the program executed by the CPU 1. This makes it possible to provide a powerful debugging means that is not possible with the prior art, which allows debugging in the actual operating state.

The information indicating the machine cycles not in use of the data bus to be output to the control line 1000 used in the above embodiment is obtained by using the output of the instruction decoder and the machine clock inside the CPU 1, and combining these by appropriate logical operations. It can be easily generated by In addition, in single-chip microcomputers using CMOS, such a signal often already exists as a means to avoid excessive current consumption due to data bus floating when the data bus is not in use. It can be output and used as is.

Note that the above is an example of the present invention, and the present invention is not limited to the above example.

For example, the data register 4 does not necessarily need to be provided inside the chip, and may be written to an external register using a control signal from the line 1000.

Alternatively, as shown in FIG. 2, two registers 6 and 7 constituting a parallel shift register and a comparator 8 for comparing the contents of the two are provided inside, and the contents of the data memory 2 are read out. The register 7 stores the read data for each
and the contents of the register 6 that stores the currently read data, and if a mismatch occurs, a mismatch signal is output from the line 8000, thereby reading the content of the specified address in the data memory 2. It is also possible to detect that a change has occurred. Although this makes the evaluation chip a little more complex, it is possible to reduce the number of external output terminals.

Furthermore, instead of inputting the monitor address directly from the outside via the line 3000, a register for storing the monitor address is input to the chip 10.
, so that the CPU 1 can write an arbitrary address of the data memory 2 into this monitor address storage register via the data bus 2100, and supply the output of this register to the multiplexer 3 via the line 3000. It can also be done. In this case, at the beginning of debugging, the address of the data memory 2 to be read may be written into this monitor address storage register using a program. By doing so, the evaluation chip becomes a little more complicated, but the number of external terminals can be reduced accordingly.

In the above embodiments, the case where the present invention is applied to an evaluation chip has been described in detail, but it goes without saying that the present invention can also be applied to a single-chip microcomputer itself as a final product.

〔Effect of the invention〕

As described above, by using the present invention, there is a means for reading out the contents of a specified address of a data memory provided on the same semiconductor substrate as the CPU in real time without affecting the normal operation of the CPU at all. can be provided. This enables debugging in the actual operating state of a device that is controlled in real time by a single-chip microcomputer, providing a powerful debugging means that was not possible with the prior art.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
and FIG. 2 is a block diagram showing some details of another embodiment. 1...CPU, 2...Data memory, 3...Multiplexer, 4...Data register, 5...Program memory, 6, 7...Register, 8...Comparator, 10...For single-chip microcomputer evaluation Chip.

Claims (1)

[Claims] 1 At least a RAM and a CPU are provided on the same semiconductor substrate, and data processed by the CPU is stored in the RAM via a data bus, or
In a microcomputer device that reads the contents of RAM and processes it with the CPU, the CPU
a control signal line that transmits a machine cycle control signal indicating that the data bus is in an unused machine cycle state, and a monitor address that specifies the address of the RAM regardless of the instruction executed by the CPU. a monitor address input line to be input, and an address selection circuit that selects the monitor address input line as an address input of the RAM according to the machine cycle control signal;
a memory circuit that stores the contents of the RAM designated by the monitor address and output to the data bus by the machine cycle control signal; and a memory circuit that reads the contents of the memory circuit as needed in response to the machine cycle control signal; 1. A microcomputer device comprising: a test control processor provided outside the semiconductor substrate that stops the program when a change occurs.