JPH0465417B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an information processing apparatus that includes a storage device and a plurality of access devices that access the storage device, and to correct errors in data read from the storage device. The present invention relates to an information processing device in which an error correction circuit is provided for each access device.

[Prior art and problems]

FIG. 1 is a diagram showing a conventional example of an information processing device equipped with an error correction circuit, FIG. 2 is a diagram showing a data path of the information processing device shown in FIG. 1, and FIG. FIG. In the figure, 1-0 and 1-1 are memory cards, 2 is a memory controller (MC),
3 is an error correction circuit (ECC).
4-0, 4-1 and 4-2 are memory access devices, 5-1 and 5-2 are input/output devices, 6-
0 is an address register, 7-0 is a read data register, 8-0 is a memory element, DV0 to DV3 are drivers, and RV0 to RV3 are receivers.

In FIG. 1, memory access device 4-
0, 4-1 and 4-2 are processors, IO controllers, etc., which can access any memory cards 1-0, 1-1 through the memory controller 2. The memory controller 2 includes an error correction circuit 3, and if there is an error in the data when reading data from the memory cards 1-0 and 1-1, the error correction circuit 3 corrects the error. correct. FIG. 2 shows the data path when the memory access device 4-0 reads data from the memory card 1-0, and FIG. 3 shows the memory access time. Memory access device 4-0
When reading data from the memory card 1-0, the address information output from the address register 6-0 is sent to the memory controller 2 through the interface B, and is sent to the receiver RV1 in the memory controller 2. , driver DV
2 to the memory card 1-0. The memory card 1-0 accesses the memory element 8-0 based on the address information and sends read data to the memory controller 2. The read data sent to the memory controller 2 is checked by the error correction circuit 3 to see if there is an error, and if there is an error, it is corrected and sent to the memory access device that is the access source. Sent to 4-0. The memory access device 4-0 stores the read data sent from the memory controller 2 in the read data register 7-0, and ends the memory cycle. In general, memory access time, that is, address information is sent from address register 6-0 and read
The time it takes to receive data into data register 7-0 is set to a constant value. The clock interval determines this time. In Figure 3, T _A is the clock interval and a is the delay and driver of address register 6-0.
DV0, DV2 delay and receiver RV1, RV
The total time with the delay of 3, b is the memory element 8-
0 access time, c is the delay time of driver DV3 and receiver RV2, d is the error correction time of the error correction circuit, e is the delay of driver DV1, the delay of receiver RV0, and read data.
This is the total time taken to set up register 7-0. The conventional example described above has several problems as follows.

The memory cycle (period T _A ) is longer because it includes the correction time d by the error correction circuit 3;
The number of times that all memory access devices 4-0, 4-1 and 4-2 use memory cards 1-0 and 1-1 (memory throughput) is limited. Memory throughput = 1/ _TA times.

Access time is longer because it passes through two interfaces A and B.

A single failure of driver DV1 and receiver RV0 of interface B causes a data error.

Since memory access always passes through the error correction circuit 3, the access time becomes long.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
In information processing equipment where storage devices are now accessed by multiple memory access devices, improvements in memory system usage efficiency, troubleshooting of interface signal lines and drivers/receivers, reduction of interface delay, and error correction. It is an object of the present invention to provide an information processing device that can efficiently correct errors in a storage device by reducing access time by equivalently shortening the access time.

[Structure of the invention]

Therefore, the information processing device of the present invention includes: a plurality of memory cards, a plurality of memory access devices, and one interface that connects the plurality of memory cards and the plurality of memory access devices. In an information processing device, the plural memory access devices include a memory access device that sends continuous data to subordinate input/output devices, and a memory access device that accesses data in units of data.
The memory access device, which sends continuous data to the underlying input/output device, consists of an address register connected to the interface via a driver, and a memory register connected to the interface via a receiver. It has at least a data register, an error correction circuit that detects and corrects errors in the data in the memory data register, and a read data register in which data output from the error correction circuit is set, and the data is read from the memory card. The read data from the memory card is sent to the input/output device via the memory data register, error correction circuit, and read data register, and when the read data from the memory card is set to the memory data register. , the memory access device is configured to send the next access request to the memory card, and performs access in units of data. a memory data register connected to the interface, an error correction circuit that detects and corrects errors in data in the memory data register, and a read data register in which data output from the error correction circuit is set; It has a selector into which the output of the memory data register and the output of the read data register are input, and when read data from the memory card is set in the memory data register, the memory is immediately
The data in the data register is output from the selector and sent to the error correction circuit, and when an error is detected by the error correction circuit, the read data
The device is characterized in that it is configured to output register data from a selector.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a diagram showing the configuration of one embodiment of the present invention, and FIG.
FIG. 6 is a diagram showing a detailed embodiment of a memory access device, FIG. 6 is a diagram explaining access time,
FIG. 7 is a diagram illustrating an example in which a plurality of words are successively accessed, and FIG. 8 is a diagram illustrating processing when there is an error and when there is no error. Figures 4 and 5
In the figure, 1-0, 1-1, 4-0 or 4-
2,5-1,5-2,6-0,7-0,8-0,
DV0, DV1, RV0 and RV1 are shown in Figures 1 and 2.
The components corresponding to those shown in the figure are shown, with reference numerals 9-0 to 9-2 indicating error correction circuits, 10-0 indicating a memory data register, and 11-0 indicating a selector.

In FIG. 4, memory access device 4-0
to 4-2 are error correction circuits 9-0 to 9-
2, and the memory is connected through interface C.
Access cards 1-0 and 1-1. Therefore,
Memory access device 4-0 is memory card 1
When reading data from -0, as shown in FIG. 5, the address information is sent from the address register 6-0, and the process until the memory element 8-0 is accessed is different from the conventional one shown in FIG. There is no difference other than the reduction in the number of interfaces, but the read data read from the memory element 8-0 passes through the driver DV1 and the receiver RV0 to the memory of the memory access device 4-0 that is the access source.
Data register 10-0 is set, at which point the memory cycle is complete. In other words, other memory devices including the memory access device 4-0
Access devices 4-1 and 4-2 can also access memory cards 1-0 and 1-1 from this point on. FIG. 6 shows this access time. In Figure 6, T _B is the clock interval and α is the address register 6-
The total time of the delay of 0, the delay of driver DV0, and the delay of receiver RV1, β is the delay time of memory element 8-0, and γ is the delay of driver DV1.
The total time of the delay of receiver RV0 and the setup of memory data register 10-0, δ is
This is the total time of the -0 delay, the error correction time of the error correction circuit 9-0, and the setup time of the read data register 7-0.

In the present invention, as is clear from comparing the access time shown in FIG. 6 with the access time shown in FIG. 3, the memory cycle is shortened by T _A - T _B , and the memory throughput is ( 1/B-1/
A) Improve. In addition, each memory access device 4
Since error correction circuits 9-0 to 9-2 are provided for each memory access device 4-0 to 4-2,
-0 to 4-2, the error correction method can be selected depending on the characteristics.

For example, sequential access devices, mainly IO controllers, have memory access time limits, and if the time limits are not respected, overruns may occur, but the access frequency is medium or small. As shown in Figure 7, such an access device relatively shortens error correction time by accessing multiple words of data at once and pipelines memory cycles and error correction time. be able to. 7th
The access time T _D for 5 words shown in the figure is 5T _B
+T _C , and the error correction time per word is
It becomes T _C /5.

In addition, random access devices such as processors have long memory access time limits.
Frequently accessed. In such an access device, there is not much merit even if it is pipelined, and the main factor for improving performance is to shorten the access time for each word. Therefore, when applying the present invention, data that is not passed through the error correction circuit, that is, data stored in the memory data register 10-0 shown in FIG. As shown in Figure 8),
An error check is performed in parallel. And an error is detected (although the probability of occurrence is quite low)
In this case, it takes more time than usual to receive the corrected data (' shown in FIG. 8) through processor exception handling, clock extension control, and the like. That is, in the case shown in FIG. 8, the memory data shown in FIG.
The contents of register 10-0 are output as read data RD from selector 11-0.
The contents of register 7-0 are output from selector 11-0 as read data RD. For example, if an error is detected by the error correction circuit 9-0, the selector 11-0 interrupts processor processing and outputs read data RD after error correction.
What is necessary is to perform control of 0.

In the configuration shown in FIG. 4, as a control method when there is a memory access request from a plurality of memory access devices 4-0 to 4-2, conventionally, the request control circuit is connected to each of the memory access devices. Various methods are already known, such as a method in which the memory is provided in the memory access device and a method in which the memory is provided in common in memory access devices, and it goes without saying that these methods may be applied. For example, as an example of the former method, there is a method in which the request control circuit has priority information between each device, and the request control circuit of each device checks whether there is an access request from another device according to the priority information and accesses it. The latter method includes a daisy chain method and a polling method, in which access requests from each device are viewed by a common request control circuit, and the request control circuit controls access requests from each device according to predetermined priority information. , independent request control method, etc. The present invention may adopt any of these methods,
Further, a method other than the method described above may also be adopted and is not particularly limited, so further detailed explanation will be omitted.

Effects of the Invention As is clear from the above description, according to the present invention, a memory access device such as a processor that accesses data in units of data, and a memory access device such as an input/output control device that performs continuous access. In addition to providing optimal error correction circuits for each of the The time can be equivalently reduced, the access time can be shortened, and the usage efficiency of the memory system can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example of an information processing device equipped with an error correction circuit, FIG. 2 is a diagram showing a data path of the information processing device shown in FIG. 1, and FIG. 4 is a diagram showing the configuration of one embodiment of the present invention, FIG. 5 is a diagram showing a detailed embodiment of the memory access device, and FIG. 6 is a diagram illustrating the access time according to the present invention. Figure, 7th
The figure is a diagram for explaining an example in which a plurality of words are accessed consecutively, and FIG. 8 is a diagram for explaining the processing when there is an error and when there is no error. 1-0 and 1-1...memory card, 2...memory controller, 3 and 9-0 or 9-2...
...error correction circuit, 4-0 to 4-2...memory access device, 5-1 and 5-2...input/output device, 6-0...address register, 7-0...
Read data register, 8-0...Memory element, 10-0...Memory data register, 1
1-0...Selector, DV0 to DV3...Driver, RV0 to RV3...Receiver.

Claims (1)

[Claims] 1. An information processing device comprising a plurality of memory cards, a plurality of memory access devices, and one interface that connects the plurality of memory cards and the plurality of memory access devices. The plural memory access devices include a memory access device that sends continuous data to a subordinate input/output device, and a memory access device that accesses data in units of data.
The memory access device, which sends continuous data to the underlying input/output device, consists of an address register connected to the interface via a driver, and a memory register connected to the interface via a receiver. It has at least a data register, an error correction circuit that detects and corrects errors in the data in the memory data register, and a read data register in which data output from the error correction circuit is set, and the data is read from the memory card. The read data from the memory card is sent to the input/output device via the memory data register, error correction circuit, and read data register, and when the read data from the memory card is set to the memory data register. , the memory access device is configured to send the next access request to the memory card, and performs access in units of data. a memory data register connected to the interface, an error correction circuit that detects and corrects errors in data in the memory data register, and a read data register in which data output from the error correction circuit is set; It has a selector into which the output of the memory data register and the output of the read data register are input, and when read data from the memory card is set in the memory data register, the memory is immediately
The data in the data register is output from the selector and sent to the error correction circuit, and when an error is detected by the error correction circuit, the read data
An information processing device configured to output register data from a selector.