JPH0465444U - - Google Patents
Info
- Publication number
- JPH0465444U JPH0465444U JP10790090U JP10790090U JPH0465444U JP H0465444 U JPH0465444 U JP H0465444U JP 10790090 U JP10790090 U JP 10790090U JP 10790090 U JP10790090 U JP 10790090U JP H0465444 U JPH0465444 U JP H0465444U
- Authority
- JP
- Japan
- Prior art keywords
- stage
- base
- lower stage
- slide shaft
- upper stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000523 sample Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
第１図及び第２図は、本考案の実施例を示した
正面図。第３図は、従来のテストハンドリング装
置による方法を示した斜視図。
１は上ステージ、２は下ステージ、３はベース
、４はプローブカード取付台、５はテープ受台、
６はピローブカード、７は接触子、８はテープ、
９は下ステージアクチユエータ、１０は上ステー
ジアクチユエータ、１１はスライド軸、１２はテ
ープ送りスプロケツト、１３はアクチユエータ。
1 and 2 are front views showing an embodiment of the present invention. FIG. 3 is a perspective view showing a method using a conventional test handling device. 1 is the upper stage, 2 is the lower stage, 3 is the base, 4 is the probe card mount, 5 is the tape holder,
6 is a pillow card, 7 is a contact, 8 is a tape,
9 is a lower stage actuator, 10 is an upper stage actuator, 11 is a slide shaft, 12 is a tape feed sprocket, and 13 is an actuator.
Claims (1)
ドリング装置において、 ベース３に対して摺動自由なスライド軸１１
の一端を固定した上ステージ１と該スライド軸１
１に対して摺動自由な下ステージ２を設ける。 スライド軸１１は、ベース３に設けた上ステ
ージアクチユエータ１０に接続される。 下ステージ２はベース３に設けた下ステージ
アクチユエータ９に接続される。 上ステージ１および下ステージ２には、同一
の部品が取り付けられるようになつている。 以上の如く構成された半導体用テスト装置。[Scope of Claim for Utility Model Registration] In a tape carrier package type test handling device, a slide shaft 11 that can freely slide with respect to a base 3 is provided.
The upper stage 1 with one end fixed and the slide shaft 1
A lower stage 2 that can freely slide relative to the stage 1 is provided. The slide shaft 11 is connected to an upper stage actuator 10 provided on the base 3. The lower stage 2 is connected to a lower stage actuator 9 provided on the base 3. The same parts are attached to the upper stage 1 and the lower stage 2. A semiconductor test device configured as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10790090U JPH0465444U (en) | 1990-10-15 | 1990-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10790090U JPH0465444U (en) | 1990-10-15 | 1990-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0465444U true JPH0465444U (en) | 1992-06-08 |
Family
ID=31854626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10790090U Pending JPH0465444U (en) | 1990-10-15 | 1990-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0465444U (en) |
-
1990
- 1990-10-15 JP JP10790090U patent/JPH0465444U/ja active Pending
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