JPH0467685A - Manufacture of nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a nonvolatile semiconductor memory device having a floating gate, it is necessary to align the floating gate over a region that becomes a channel of a MISFET that is a memory cell and form it by photolithography. In order to improve the degree of integration by eliminating the need for a semiconductor substrate, a first insulating film is formed on a semiconductor substrate of a first conductivity type, an electrically floating first gate is formed on the first insulating film, and a first electrically floating gate is formed on the first insulating film. 2 forming an insulating layer film,
A second gate having an external electrode is formed thereon, and a source and a drain are formed on the surface of the semiconductor substrate and are formed of regions of a conductivity type opposite to the first conductivity type, which face each other with the first gate and the second gate interposed therebetween. In a method of manufacturing a nonvolatile semiconductor memory device in which a channel region is formed between a source and a drain, a first insulating film is grown, a conductor forming a first gate is formed thereon, and a conductor is formed in a predetermined manner. After shaping into the shape,
A channel region was formed in a self-aligned manner by growing a thick field insulating film in a portion where there is no conductor.

[Industrial application field]

The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device having a floating gate.

In recent years, semiconductor memory devices have grown from 1 Mbit to 4 bits on one chip.
Although it has come to have a memory capacity of M focus, the demand for further increasing the memory capacity is becoming stronger and stronger.

In general, semiconductor memory devices are required to have smaller chip sizes to reduce costs, and nonvolatile semiconductor memory devices are no exception. It is required to reduce the area of

[Conventional technology]

Conventionally, as a nonvolatile semiconductor memory device, a MISFET type device having a floating gate (FC) and a control gate (CC) capacitively coupled to the floating gate (FC) is known.

FIG. 2 is a configuration diagram of one memory cell of a nonvolatile semiconductor memory device, in which (a) is a top view, (b) is a cross-sectional view taken along the line A-A'', and (c) is the BB'' line. FIG.

In the figure, 1 is a P-type silicon substrate, 2 is an n-type source, 3 is an n-type drain, 4 is a channel, and 5 is a thickness of 300 mm.
Gate insulating film made of irregular SiO□, 6 has a thickness of 70
7 is a floating gate made of polysilicon, 8 is an insulating film of irregular SiO□ or the like with a thickness of about 300, and 9 is a control gate made of polysilicon.

As described above, this nonvolatile semiconductor memory device has a structure in which a floating gate is provided below the gate of the n-channel MISFET.

The operation of this semiconductor memory device is as follows.

Erasing When the floating gate 7 of this device is irradiated with ultraviolet rays, the electrons stored there are released and the charge on the floating gate becomes zero.

In this state, if an appropriate voltage is applied to the control gate 9, the MISFET becomes conductive, but this is not controlled by the information “
1'.

In this way, the information in all memory cells is pulsed from “0”.
``” is erasure.

When a high voltage is applied to the write control gate 9 and the drain 3, AVALANCHE BREAK DOWN occurs, and a portion of the high-energy electrons are captured by the floating gate 7 and accumulated there.

In this state, negative charges are accumulated in the floating gate 7, so even if an appropriate operating voltage is applied to the control gate 9, the MISFET will not conduct.

This is defined as information "0".

Writing is the process of changing only a predetermined memory cell from a state in which all memory cells are "1'°" to "0" due to erasing.

Next, a conventional method of manufacturing this semiconductor memory device will be explained.

FIG. 3 is a manufacturing process diagram of a conventional nonvolatile semiconductor memory device.

The manufacturing method will be explained with reference to this process diagram.

Note that the ordinal numbers of the steps in this description correspond to the numbers in Figure 3; the figures in the left column are cross-sectional views of two memory cells taken at the center perpendicular to the channels, and the figures in the right column are 1. FIG. 3 is a cross-sectional view taken along the center of one memory cell in the direction of its channel;

First step Protective Si is placed on the p-type silicon substrate 11 with low impurity concentration.
n. The film 12 is grown by thermal oxidation.

2nd process A 2Si, N, film 13 is grown on the SiO2 film 12.

Third step S i3 A photoresist (PR) 14 is applied to the N4 film 13 .

Fourth step: Using a mask, the photoresist is exposed and developed so that the photoresist 14 corresponding to the regions (transistor regions) that will become the drain, channel, and source of the MISFET in the future remains.

Fifth step The S1*Na film 13 is
selectively etched.

6th step 5ii The photoresist 14 on the N4 film 13 is removed.

In the seventh field oxidation step, a thick SiO□ film 15 is grown in the region covered with the 5j3N4 film 13, that is, in areas other than the transistor region. At this time, oxygen flows around to the edge of the Si, N4 film 13, so that a slight amount of 5iOz grows, and that part is called a bird's beak.

8th process 5ii All the N4 film 13 is removed.

In the ninth step Sin, the film 13 is thinly removed. Therefore, the oxide film 12 in the gate region disappears.

Tenth step: Oxidation is performed again to grow a high-quality SiO□ film 16 to serve as a gate insulating film.

11th step A first polysilicon layer 17 is grown over the entire top surface.

12th step A photoresist 18 is applied to the entire surface.

Thirteenth step: Using a mask, the photoresist is exposed and developed so that the photoresist 18 in the region that will become the channel of the MISFET remains.

At this time, a positioning margin is required so that the first polysilicon layer 17 completely covers the channel region of the MISFET.

The first polysilicon layer 17 is locally etched using the remaining photoresist 18 in the fourteenth step.

15th step Strip the photoresist layer 18.

16th step Oxidation is performed to grow a SiO□ film 19.

17th step A second polysilicon layer 20 is grown over the entire top surface.

18th step A photoresist 21 is applied to the entire upper surface.

The 19th step is exposed and developed using a mask so that the photoresist 21 remains only in the portion that will become the control gate.

Using the photoresist 21 remaining in the 20th step as a mask, the second polysilicon layer 20, the first polysilicon layer 17, and the Sin film therebetween are removed by etching.

21st process The photoresist 21 is peeled off.

Twenty-second step: Oxidation is performed again to form an oxide film 22 on the surface of the second polysilicon layer 20.

Twenty-third step: As''' is selectively ion-implanted to form n-type regions that will become the source 23 and drain 24.

[Problem to be solved by the invention]

In the conventional manufacturing method, when the photoresist 18 other than the area that will become the channel of the MISFET is exposed and developed using a mask in the 13th step described above, a margin is required for safe alignment. , this will lead to a corresponding decrease in the degree of integration.

The present invention aims to eliminate the need for this margin for alignment and increase the degree of integration.

[Means to solve the problem]

According to the present invention, a first insulating film is formed on a semiconductor substrate of a first conductivity type, and an electrically floating first insulating film is formed on the first insulating film.
forming a gate, forming a second insulating layer thereon, forming a second gate having an external electrode thereon, and facing the semiconductor substrate surface with the first gate and the second gate interposed therebetween; In a method for manufacturing a non-volatile semiconductor memory device in which a source and a drain are formed from regions of a conductivity type opposite to a first conductivity type, and a channel region is formed between the source and the drain, a first insulating film is grown. After that, a conductor that forms the first gate is formed thereon, and after shaping into a predetermined shape, a channel region is formed in a self-aligned manner by growing a thick field insulating film in the area where the conductor is not present. I decided to do so.

[Effect]

After growing the first insulating film, growing a conductor to form the first gate on it and shaping it into a predetermined shape using photolithography technology, etc., then growing a thick field insulating film in the area where the conductor is not present. In this case, the channel region is formed in a self-aligned manner, and mask alignment becomes unnecessary.

〔Example〕

Hereinafter, a manufacturing method of an embodiment of the present invention will be explained based on the drawings.

FIG. 1 is a process diagram for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

The manufacturing method of the embodiment of the present invention will be explained with reference to this process diagram.

As with the explanation of the conventional manufacturing method using FIG. 3, the ordinal numbers of the steps in this explanation correspond to the numbers in FIG. Figures 1A and 1B are cross-sectional views of two memory cells, with the right column of figures being cross-sectional views taken along the center of one memory cell in the direction of its channel.

First step: A SiO□ film 32 is grown on a P-type silicon substrate 31.

This corresponds to the first step in the conventional manufacturing method, but in the conventional example, the film quality was not an issue because it was for protection, but in this example, it is used as a gate insulating film later, so a good oxide film is required. It must be.

Second step: A polysilicon film 33 is grown on the entire surface of the 5in2 film 32.

Third step: A S I 3 N 4 film 34 is grown on the polysilicon film 33 .

Fourth step: A photoresist layer (PR) 35 is applied on the Si3Ng film 34.

Exposure of the photoresist (PR) layer 35 using the fifth process mask,
After development, the future MI of the photoresist (PR) layer 35 is
Only the regions that will become the train, channel, and source of the SFET, ie, the transistor regions, are left.

Due to the photoresist (PR) layer 35 remaining in the sixth etching process, selective S]:l N4 film 34 and polysilicon film 33, S
The iO□ film 32 is etched.

7th step The photoresist (PR) layer 35 is peeled off.

In an eighth step field oxidation step, a thick Si film 36 is grown in the region covered with the Si N4 film 34, that is, in a region other than the transistor region.

At this time, since oxygen also flows around to the edge of the Si, N4 film 34, a small amount of SiO2 grows in that area as well.

This part is called the bird's beak because of its cross-sectional shape.

Ninth step: The Si, N, and film 34 are completely removed, and the 5in2 film 36 is slightly etched.

10th Step This step and subsequent steps are the same as the 16th step and subsequent steps explained in FIG. 3 as a conventional manufacturing method.

〔Effect of the invention〕

In the conventional manufacturing method, the alignment margin of the mask in photolithography for etching the polysilicon layer that will become the first gate is required to be, for example, 0.5 μm.

Therefore, the size of the memory cell of a 4 Mbit nonvolatile semiconductor memory device was 2.6 x 2.6 μm2, but according to the present invention, there is no need for alignment margin, so 1.
The size is 6×2.6 μm2, and the area can be reduced by about 60%.

[Brief explanation of drawings]

Figures 1 (1) to (9) are manufacturing process diagrams of a nonvolatile semiconductor memory device according to an embodiment of the present invention, and Figures 2 (a), (b), and (C
) is a configuration diagram of one memory cell of a nonvolatile semiconductor memory device,
FIGS. 3(1) to 3(23) are manufacturing process diagrams of a conventional nonvolatile semiconductor memory device. 31-.-P type silicon substrate, 32-3 iO□ film,
33-polysilicon film, 34-3 t3N4 film, 3
5 Photoresist layer (PR), 36-thick SiO□ film Figure 1 (Part 2) Figure 1 (Part 1) Figure 3 (Part 1) Figure 3 (Part 2) Nu role Figure 3 (Part 3) ]] Figure 3 (Part 4) Figure 3 (Part 5)

Claims (1)

[Claims] forming a first insulating film on a semiconductor substrate of a first conductivity type, forming an electrically floating first gate thereon;
A second insulating layer film is formed thereon, a second gate having an external electrode is formed thereon, and a first conductivity type film is formed on the surface of the semiconductor substrate, facing each other with the first gate and the second gate interposed therebetween. In a method for manufacturing a nonvolatile semiconductor memory device in which a source and a drain are formed from regions of conductivity type opposite to that of the first insulating film, a channel region is formed between the source and the drain. 1. After forming a conductor forming one gate and shaping it into a predetermined shape, a channel region is formed in a self-aligned manner by growing a thick field insulating film in a portion where the conductor is not present. A method for manufacturing a nonvolatile semiconductor memory device.