JPH046827A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an manufacturing method which can solve problems such as a drop in a breakdown strength when a P-type buried layer collides with an N-type buried layer by a method wherein an SiO2 film and an Si3N4 film are formed on a substrate, an opening part is formed in the Si3N4 film, impurities are introduced, the SiO2 film is removed, silicon is grown selectively, the Si3N4 film is removed and second impurities are introduced. CONSTITUTION:The following processes are included: a process where an SiO2 film 102 and an Si3N4 film 103 are formed sequentially on a semiconductor substrate 101 of a first conductivity type and an opening part 103A is formed in a prescribed part of the Si3N4 film 103; a process where impurity ions of the first conductivity type are implanted by making use of said Si3N4 film 103 as a mask and a diffusion layer 104 of the first conductivity type is formed in the semiconductor substrate 101; a process where the SiO2 film 102 on said diffusion layer 104 of the first conductivity type is removed, silicon 105 is grown selectively in the transverse direction of the Si3N4 film 103 and the Si3N4 film 103 is removed; and a process where impurity ions of a second conductivity type are implanted by making use of said silicon 105 as a mask and a diffusion layer 106 of the second conductivity type is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having both a P-type impurity layer and an N-type impurity layer as buried layers.

(Prior Art) In recent years, BiCMO3 mixed mounting technology has been increasingly used for the purpose of speeding up analog/digital mixed mounting and 0MO5, and has become the mainstream in the field of composite technology.

Since Bi CMO3LSI combines the characteristics of bipolar and CMO3, it can achieve excellent performance such as high speed, high integration, high voltage resistance, high load driving ability, and low power consumption, but it is structurally equipped with bipolar elements. for,
Epitaxial layers and isolation diffusions are required.

In addition, since the bipolar and 0MO3 elements are simultaneously formed without impairing their performance, the process is complicated and the number of masks increases, which is disadvantageous from an economic point of view.

Here, a conventional method for manufacturing a Bi CMO3 type semiconductor integrated circuit will be explained with reference to FIG. In this figure 2,
A N buried layer 2 is formed on a P-type semiconductor substrate 1,
This N buried layer 2 is an NPN bipolar transistor 10.
Usually As or S is used to lower the collector series resistance of 0.
It is diffused to 20-100Ω10 using b. A method for manufacturing the NPN bipolar transistor 100 is described in Japanese Patent Laid-Open No. 102259/1983.

The N buried layer 2 is also simultaneously diffused into the PMO 5300 formation region so that the CMO 5 does not cause parasitic bipolar operation.

Reference numeral 4 denotes a P buried layer, which is formed in advance in the element isolation region of the NPN bipolar transistor 100 by an ion implantation method, etc., and utilizes upward diffusion from the semiconductor substrate 1 during the epitaxial layer formation and isolation diffusion in the next process. It is used to shorten the separation and diffusion time, and is usually set to 50 to 300 Ω/mouth using B (poron).

Further, in order to prevent the NMO 3200 from causing a parasitic bipolar operation, it is also formed in the NMO 3200 formation region at the same time.

The concentration and thickness of the N-epitaxial layer 5 are determined so that the device characteristics of the NPN bipolar transistor 100 and the gate threshold voltage of PMO3 can be controlled.

P-diffusion region 6 is an NPN bipolar transistor 100
It is diffused from the surface of the N-epitaxial layer 5 in order to isolate the elements and control the threshold voltage of the NMO 3200.

7 is a P diffusion layer, which is an NPN bipolar transistor 100
active base, 8 is the P diffusion layer, PMO3
The source, drain, and inactive base layer of the NPN bipolar transistor 100 are formed. The inactive base layer is necessary to make ohmic contact with the base layer.

Reference numeral 9 denotes an N9 diffusion layer, which forms contacts for the source and drain of the NMO 3200 and the emitter and collector layers of the NPN bipolar transistor 100.

The P diffusion layer 7, the P'' diffusion layer 8, and the N'' diffusion layer 9 are oxidized with Wi11 so as to form P, P'', and It'' areas, respectively.
Select as a mask to be diffused. 10 is PMO5NMO
5 gate.

In this way, a BiCMO3 type semiconductor integrated circuit is constructed, but the steps after the formation of the N-epitaxial layer 5 are only an active base layer forming step added to the normal CMO3 manufacturing process, and most of the steps are are formed at the same time.

Therefore, in order to pursue economic efficiency in the manufacturing process of BiCMO3 type integrated circuits, it is essential to simplify the process before forming the epitaxial layer.

In addition, as a more improved process, as described on page 75 of the November 1986 issue of Nikkei Microdevice, the part where the P buried layer 4 is to be formed is first covered with an s;sNa film, and then this 5iJaWA as a mask N
SB for the 0 buried layer is implanted using ion implantation silane.

Next, we conduct a drive-in in an oxidizing atmosphere, and
After forming a thick oxide film in the region where sb was implanted, Si
After peeling off the 3Ns film, there was a method of implanting and driving in P for the buried layer.

(Problem to be solved by the invention) However, the Nikkei Microdevice 1986/1
The method described on page 75 of the January issue forms the N'' layer and the P'' layer using one mask, but the N'' buried layer and the P'' buried layer are therefore Collision in the area, - boat fishing concentration (N"-10"1ons / al!, p"...
・10''' 1 ons/cd), the breakdown voltage is at most about IOV, and it is not possible to form an element with a higher breakdown voltage.

In addition, if the P゛ buried layer and the N° buried layer are formed using one mask each, it is possible to separate the second layer and the N layer, so a high breakdown voltage can be achieved. In addition, two masks are required, and misalignment of the two masks must be taken into account, which poses a problem in that it hinders miniaturization.

This invention solves the problems of the above-mentioned prior art.
The breakdown voltage decreases due to collision between the type buried layer and the N type buried layer, and when the P' buried layer and the N' buried layer are formed using one mask each, two masks are used. The present invention provides a method for manufacturing a semiconductor device that requires a large number of semiconductor devices and that solves the problem of preventing downsizing due to misalignment of masks.

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device, in which a SiO□ film and 5iJa 11 are formed on a semiconductor substrate, and SiO□ film and 5iJa 11 are formed on a semiconductor substrate.
After forming an opening of NnM and introducing the first impurity using the 5isNn film as a mask, a step of removing 5iOzll using the SiJ film as a mask, and laterally forming the opening on the Si base and on the 5isNn bl. This method introduces a step of growing silicon single crystal or polycrystalline silicon, removing the 5iJa film, and introducing a second impurity into the entire surface.

(Function) According to the present invention, since the above steps are introduced in the method for manufacturing a semiconductor device, an opening is formed in the 5isN4 film and impurity ions of the same conductivity type as the semiconductor substrate are implanted, and the first After forming a diffusion layer of
! The second diffusion layer can be formed at a predetermined distance from the first diffusion layer by removing ions of the conductivity type opposite to the semiconductor iFi using single crystal silicon or polycrystalline silicon as a mask. Problems can be removed.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1 (4) to Figure 1 T
fl is a process sectional view of one embodiment.

First, as shown in FIG.
200-300 using known thermal oxidation technology on the surface of 01.
A SiJ film 102 of about 1,000 layers is formed, and then about 1000 layers of O5iJ411103 are formed using a known CVD technique.

Next, as shown in Figure 1 (bl), a hot phosphoric acid solution or C
Known photolithography, such as using F4+0□ plasma,
Using an etching technique, a window is formed in the Si3N4 film 103 to form an opening 103A.

Furthermore, using the opened St, N4 film 103 as a mask, P-type impurities are introduced into the opening 103A using a known ion introduction method.

However, at this time, the energy of the ions needs to pass through 200 to 300 SiJ membranes 102, so 40 to 5
0KeV dose is 5 x 10”1ons/-
As a result, a P-type impurity diffusion layer 104 is obtained.

Next, using a known wet etching technique using an IP buffer solution, etc., the opening 1 is etched as shown in FIG.
The Stow film 102 of 03A is removed.

Next, as shown in FIG. 1(dl), silicon is selectively grown only in the opening 103A on the P-type impurity diffusion layer 104 using a known CVD technique.

This silicon may be single crystal silicon or polycrystal silicon.

For example, for single crystal silicon, “GrowthP”
rocess of 5ilicon 0ver 5i
O1by CVD: Epitaxial Late
ral Overgrowth Technique
: J, Electr.

chew, Soc, : 5olid-3tate
5science and technology.

1o1y: 1050°C, 5iHzC1t=0.
751 /sin, HCI = 21 /@in, H
By growing at z = 1801/win, selective and further lateral growth of the opening can be obtained.

For example, if silicon is grown to a thickness of 3 microns, growth of about 3 to 5 microns can be obtained in the lateral direction. This lateral growth dimension is for forming an N-type diffusion layer, which will be described later, at a distance from the P-type impurity diffusion layer 104.

Next, as shown in FIG. 1 (el), 5ixN
a Tll 103 is completely removed, and using known ion introduction technology, 40KeV dose 2Xl0ISi
An N-type impurity is introduced with an energy of about ons/- to form the above-mentioned N-type diffusion layer 106.

At this time, since the N-type impurity is not introduced into the lateral growth portion of the silicon 105, a distance of 3 to 5 cm is created between the P-type impurity diffusion layer 104 and the N-type diffusion layer 106.

Thereafter, the silicon 105 is removed by etching, for example, the following method can be considered. The entire surface is coated with a resist that has an etching rate very close to that of silicon, and the well-known R
After etching the silicon and resist using IE technology and etching with an appropriate device (when the remaining amount of silicon is 200
0 to 3000 people) Remove the resist, perform thermal oxidation,
After all the silicon is reduced to 5 tozll, the entire SiO□ film is removed using an OF buffer solution or the like.

After that, heat treatment is performed at 1100°C to 1200°C, and as shown in FIG.
The type diffusion layer 106 is made to have a desired diffusion layer depth and a predetermined resistivity.

(Effects of the Invention) As explained in detail above, according to the present invention, 5isNn II formed on a semiconductor substrate via a SiO□ film
After opening a window and forming an impurity diffusion layer of the same conductivity type on the semiconductor substrate using 5iJa II as a mask, the Si film is removed and grown in the single crystal silicon or polycrystal silicon opening, and Si3N4 is grown. By removing the film and forming a diffusion layer of the opposite conductivity type on the semiconductor substrate, the P-type impurity physical layer and the N-type impurity physical layer can be self-aligned using only one mask. This reduces the mask alignment process and simplifies the process.

Moreover, between the N-type impurity diffusion layer and the P-type impurity diffusion layer,
Since a spacer formed by lateral growth of silicon single crystal or polycrystalline silicon is inserted, a distance corresponding to the spacer is created between the two diffusion layers.

It is a well-known fact that the longer this distance is, the higher the breakdown voltage can be obtained.If the distance between the diffusion layers is about 3n, compared to about 10V shown in the conventional example, a breakdown voltage of about 40 to 50V can be expected.

[Brief explanation of drawings]

1 (al to 1ffl) are process cross-sectional views of an embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 2 is process cross-sectional views of a conventional semiconductor device manufacturing method. 101... P-type silicon substrate, 102...Sin,
Film, 103...5iJn II, 103A...Opening, 104...P type impurity diffusion layer, 105...Silicon, 106...N type diffusion layer. Agent: Hiroshi Kikuchi, Patent Attorney, Inventor
) 2nd stage cod surface diagram Figure 1 +06: # type diffusion layer 4th company e-th process continuous surface 12 Figure l

Claims (1)

[Claims] (a) A SiO_2 film and a Si_3N_4 film are sequentially formed on a semiconductor substrate having a first conductivity type, and this Si_
(b) using the Si_3N_4 film as a mask, ion-implanting an impurity having a first conductivity type to form a diffusion layer of the first conductivity type in the semiconductor substrate; (c) selectively growing silicon after removing the SiO_2 film on the first conductivity type diffusion layer;
The above Si_3N_ is grown laterally on the i_3N_4 film.
(d) ion-implanting an impurity having a second conductivity type using the silicon as a mask to form a diffusion layer of the second conductivity type. .