JPH046834A - Method of forming silicon nitride film - Google Patents

Method of forming silicon nitride film

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Publication number
JPH046834A
JPH046834A JP2107376A JP10737690A JPH046834A JP H046834 A JPH046834 A JP H046834A JP 2107376 A JP2107376 A JP 2107376A JP 10737690 A JP10737690 A JP 10737690A JP H046834 A JPH046834 A JP H046834A
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
breakdown voltage
dielectric breakdown
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2107376A
Other languages
Japanese (ja)
Inventor
Hisatoshi Mori
森 久敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2107376A priority Critical patent/JPH046834A/en
Priority to US07/690,816 priority patent/US5284789A/en
Priority to EP91106621A priority patent/EP0454100B1/en
Priority to DE69128210T priority patent/DE69128210T2/en
Priority to KR1019910006715A priority patent/KR940008356B1/en
Publication of JPH046834A publication Critical patent/JPH046834A/en
Priority to US07/975,282 priority patent/US5367179A/en
Priority to US08/004,641 priority patent/US5243202A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコン窒化膜の成膜方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a silicon nitride film.

〔従来の技術〕[Conventional technology]

シリコン窒化膜は、薄膜トランジスタやMO5型集積回
路素子のゲート絶縁膜等として用いられている。
Silicon nitride films are used as gate insulating films for thin film transistors, MO5 type integrated circuit elements, and the like.

このシリコン窒化膜は、一般にプラズマCVD装置によ
って成膜されており、従来は、RF放電のパワー密度を
120〜130 m W / c m 2程度に制御し
て、シリコン原子S+と窒素原子Nとの組成比Si /
Nが化学量論比(Si/N−0,75)より僅かに窒素
原子Nの量が多いシリコン窒化膜を成膜している。
This silicon nitride film is generally formed using a plasma CVD apparatus, and conventionally, the power density of RF discharge is controlled to about 120 to 130 mW/cm2, and silicon atoms S+ and nitrogen atoms N are combined. Composition ratio Si/
A silicon nitride film is formed in which the amount of nitrogen atoms N is slightly larger than the stoichiometric ratio (Si/N-0.75).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記従来の成膜方法で成膜されたシリコ
ン窒化膜は、絶縁破壊耐圧が悪いという問題をもってい
る。
However, the silicon nitride film formed by the conventional film forming method described above has a problem of poor dielectric breakdown voltage.

すなわち、第2図は従来の成膜方法で成膜されたシリコ
ン窒化膜の絶縁破壊耐圧ヒストグラムを示し、第3図お
よび第4図はシリコン窒化膜の絶縁破壊耐圧の測定に用
いた被検体を示している。
That is, FIG. 2 shows a breakdown voltage histogram of a silicon nitride film formed by a conventional film formation method, and FIGS. 3 and 4 show the test object used to measure the breakdown voltage of a silicon nitride film. It shows.

前記被検体は、第3図および第4図に示すように、ガラ
ス基板1面にストライプ状の下部電極2を多数本互いに
平行に形成し、その上にシリコン窒化膜3を成膜して、
このシリコン窒化膜3の上に前記下部電極2と直交する
ストライブ状の上部電極4を多数本互いに平行に形成し
たもので、シリコン窒化膜3の絶縁破壊耐圧は、各下部
電極2に順次電圧を印加し、1本の下部電極2に電圧を
印加するごとに各上部電極4に流れる電流の有無を順次
チエツクする方法により、下部電極2と上部電極4とが
交差している電極対向部の全てについて測定した。
As shown in FIGS. 3 and 4, the test object has a large number of striped lower electrodes 2 formed in parallel to each other on one surface of a glass substrate, and a silicon nitride film 3 formed thereon.
On this silicon nitride film 3, a large number of strip-shaped upper electrodes 4 are formed in parallel to each other, perpendicular to the lower electrode 2. By applying a voltage to each lower electrode 2 and sequentially checking the presence or absence of current flowing to each upper electrode 4 each time a voltage is applied to one lower electrode 2, the electrode facing portion where the lower electrode 2 and the upper electrode 4 intersect can be checked. All were measured.

なお、前記被検体としては、電極対向部の総数が691
,200、全ての電極対向部の総面積が2.07cm2
で、かつシリコン窒化膜3を、基  板  温  度 
;  250℃プロセスガス;  5IH430CCM
N H、60CCM N2  390CCM 圧        力 ;   Q、 5TorrRF
放電周波数;  13.56MH2放電パワー密度; 
127mW/cm2の成膜条件でプラズマCVD装置に
より1000人の膜厚に成膜したものを使用した。この
シリコン窒化膜3の組成比は、St/N=0.69であ
る。
In addition, as for the above-mentioned object, the total number of electrode facing parts is 691.
, 200, the total area of all electrode facing parts is 2.07 cm2
and the silicon nitride film 3 at the substrate temperature
; 250℃ process gas; 5IH430CCM
NH, 60CCM N2 390CCM Pressure; Q, 5TorrRF
Discharge frequency; 13.56MH2 discharge power density;
A film formed to a thickness of 1000 by a plasma CVD apparatus under film forming conditions of 127 mW/cm2 was used. The composition ratio of this silicon nitride film 3 is St/N=0.69.

そして、前記被検体について、電極2.4間に印加する
電界強度を連続的に変化させながら、前記シリコン窒化
膜3の絶縁破壊耐圧を測定したところ、このシリコン窒
化膜3の各印加電界強度での絶縁破壊発生率(電極対向
部の総数に対する絶縁破壊が発生した電極対向部の数の
比率)は、第2図の通りであった。なお、ここでは、l
Xl0−6A以上の電流が流れた電極対向部を絶縁破壊
を生じた不良部と判定した。
The dielectric breakdown voltage of the silicon nitride film 3 was measured for the test object while continuously changing the electric field strength applied between the electrodes 2 and 4. At each applied electric field strength of the silicon nitride film 3, The dielectric breakdown occurrence rate (ratio of the number of electrode facing parts where dielectric breakdown occurred to the total number of electrode facing parts) was as shown in FIG. In addition, here, l
The electrode facing part through which a current of X10-6 A or more flowed was determined to be a defective part where dielectric breakdown occurred.

この第2図の絶縁破壊耐圧ヒストグラムのように、従来
の成膜方法で成膜されたシリコン窒化膜は、3 M V
 / c m 2以下の弱い印加電界強度で発生するA
モード不良(ピンホールによる初期不良)が、I M 
V / c m 2で約5%、2 M V / c m
 2で約2,5%と大きな比率で発生し、また3MV/
cm2より大きな印加電界強度で発生するBモード不良
(ウィークスポットによる不良)が、5 M V / 
c m 2で約5.2%、6 M V / c m 2
て約14.3%、7 M V / c m 2で約2.
6%とかなり大きな比率で発生した。なお、第2図には
RF放電のパワー密度を127mW/cm2に制御して
成膜したシリコン窒化膜の絶縁破壊耐圧ヒストグラムを
示したが、放電パワー密度を120〜130mW/cm
2程度に制御する従来の成膜方法で成膜されたシリコン
窒化膜は、いずれも第2図とほぼ同様な絶縁破壊耐圧を
示す。
As shown in the dielectric breakdown voltage histogram in Figure 2, the silicon nitride film formed by the conventional film forming method has a dielectric breakdown voltage of 3 MV.
A generated at weak applied electric field strengths below / cm2
Mode failure (initial failure due to pinhole) is I M
Approximately 5% in V/cm2, 2MV/cm2
2 occurs at a large rate of about 2.5%, and 3MV/
B-mode defects (defects due to weak spots) that occur at applied electric field strengths greater than cm2 are 5 M V /
About 5.2% in cm2, 6 MV/cm2
about 14.3% at 7 MV/cm2, about 2.3% at 7 MV/cm2.
This occurred at a fairly large rate of 6%. Note that although Fig. 2 shows a dielectric breakdown voltage histogram of a silicon nitride film formed by controlling the power density of RF discharge to 127 mW/cm2, it is also possible to
All silicon nitride films deposited by the conventional film deposition method controlling the dielectric breakdown voltage to about 2 show dielectric breakdown voltages substantially similar to those shown in FIG.

このように、前記従来の成膜方法で成膜されたシリコン
窒化膜は、絶縁破壊耐圧か悪く、したがってこのシリコ
ン窒化膜をゲート絶縁膜とする薄膜トランジスタやMO
S型集積回路素子は、絶縁不良の発生率が高くて、製造
歩留および信頼性が低くかった。
As described above, the silicon nitride film formed by the conventional film forming method has a poor dielectric breakdown voltage, and therefore, thin film transistors and MO
S-type integrated circuit devices have a high incidence of insulation failure, and have low manufacturing yield and reliability.

本発明はこのような実情にかんがみてなされたものであ
って、その目的とするところは、高い絶縁破壊耐圧を有
するシリコン窒化膜を得ることができるシリコン窒化膜
の成膜方法を提供することにある。
The present invention has been made in view of the above circumstances, and its purpose is to provide a method for forming a silicon nitride film that can obtain a silicon nitride film having a high dielectric breakdown voltage. be.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、プラズマCVD装置によるシリコン窒化膜の
成膜において、RF放電のパワー密度を60〜100m
W/cm2に制御することを特徴とするものである。
In the present invention, when forming a silicon nitride film using a plasma CVD apparatus, the power density of RF discharge is set to 60 to 100 m.
It is characterized by being controlled to W/cm2.

〔作用〕[Effect]

このようにRF放電のパワー密度を60〜100mW/
cm2に制御して成膜したシリコン窒化膜は、その絶縁
破壊耐圧か極めて高い。
In this way, the power density of RF discharge can be increased to 60 to 100 mW/
A silicon nitride film formed with a controlled thickness of cm2 has an extremely high dielectric breakdown voltage.

〔実施例〕〔Example〕

以下、本発明の一実施例を説明する。 An embodiment of the present invention will be described below.

この実施例では、シリコン窒化膜を、 基  板  温  度 ;  250℃プロセスガス;
  SiSiH430CCH、60CCM N2    390CCM 圧        力 :   0. 5TorrRF
放電周波数;  13.56MHz放電パワー密度; 
 84mW/cm2の成膜条件でプラズマCVD装置に
より1000人の膜厚に成膜した。なお、この成膜条件
は、RF放電のパワー密度を84 m W / c m
 2とした以外は、前述した被検体のシリコン窒化膜を
従来の成膜方法で成膜したときの成膜条件と同じである
In this example, the silicon nitride film was deposited at a substrate temperature of 250°C and a process gas of 250°C.
SiSiH430CCH, 60CCM N2 390CCM Pressure: 0. 5TorrRF
Discharge frequency; 13.56MHz discharge power density;
A film was formed to a thickness of 1000 using a plasma CVD apparatus under film forming conditions of 84 mW/cm2. Note that this film formation condition reduces the power density of RF discharge to 84 mW/cm
2, the film forming conditions were the same as those used when forming the silicon nitride film of the object to be tested using the conventional film forming method.

このようにRF放電のパワー密度を84 m W /c
m2に制御して成膜したシリコン窒化膜の組成比はSt
/N−0,83であり、このシリコン窒化膜は、化学量
論比(Si /N−0,75)より若干シリコンSiの
量が多い組成となっている。
In this way, the power density of RF discharge was reduced to 84 mW/c
The composition ratio of the silicon nitride film formed by controlling m2 is St
/N-0,83, and this silicon nitride film has a composition in which the amount of silicon Si is slightly larger than the stoichiometric ratio (Si /N-0,75).

そして、前記実施例の成膜方法で成膜したシリコン窒化
膜は、Aモード不良がほとんど無く、またBモード不良
も非常に僅かな、極めて高い絶縁破壊耐圧をもっている
The silicon nitride film formed by the film forming method of the above embodiment has an extremely high dielectric breakdown voltage with almost no A-mode defects and very few B-mode defects.

すなわち、第1図は、第3図および第4図に示した被検
体のシリコン窒化膜3を前記実施例の成膜方法で成膜し
、この被検体について、電極2゜4間に印加する電界強
度を連続的に変化させながらシリコン窒化膜3の絶縁破
壊耐圧を測定した結果を示した絶縁破壊耐圧ヒストグラ
ムである。なお、この絶縁破壊耐圧の測定は、従来の成
膜方法で成膜したシリコン窒化膜の絶縁破壊耐圧測定と
同じ条件で行ない、I X 10−6A以上の電流が流
れた電極対向部を絶縁破壊を生じた不良部と判定した。
That is, in FIG. 1, the silicon nitride film 3 of the test object shown in FIGS. This is a breakdown voltage histogram showing the results of measuring the breakdown voltage of the silicon nitride film 3 while continuously changing the electric field strength. This dielectric breakdown voltage measurement was performed under the same conditions as the dielectric breakdown voltage measurement of a silicon nitride film formed by a conventional film deposition method, and the dielectric breakdown voltage was measured at the electrode facing part where a current of I x 10-6 A or more passed. This was determined to be a defective part.

この第1図の絶縁破壊耐圧ヒストグラムのように、前記
実施例の成膜方法で成膜されたシリコン窒化膜は、3M
V/cm2以下の弱い印加電界強度で発生するAモード
不良はほぼ完全に無くなっており、また3 M V /
 c m 2より大きな印加電界強度で発生するBモー
ド不良も、5 M V / c m 2で約0.4%、
6 M V / c m 2で約0,6%、7 M V
 / c m 2で約0.4%、9 M V / c 
m 2で約O13%と極めて小さい比率でしか発生しな
かった。
As shown in the dielectric breakdown voltage histogram in FIG.
A-mode defects that occur at weak applied electric field strengths of V/cm2 or less are almost completely eliminated, and 3 M V/cm2 or less
B-mode defects that occur at applied electric field strengths greater than cm2 are also approximately 0.4% at 5 MV/cm2,
Approximately 0,6% at 6 MV/cm2, 7 MV
Approximately 0.4% at /cm2, 9 MV/c
It was generated only at a very small rate of about 13% O per m 2 .

このように、前記実施例の成膜方法で成膜したシリコン
窒化膜は、その絶縁破壊耐圧が極めて高く、したがって
、このシリコン窒化膜を薄膜トランジスタやMO5型集
積回路素子のゲート絶縁膜とすれば、この薄膜トランジ
スタやMO5型集積回路素子の絶縁不良の発生率を大幅
に少なくして、その製造歩留および信頼性を向上させる
ことができるし、またゲート絶縁膜(シリコン窒化膜)
の絶縁破壊耐圧が高いためにその膜厚を薄くできるから
、ゲート電極に印加するゲート電圧が同じでも、半導体
層により強い電界をかけてオン電流を大きくとることが
できる。
As described above, the silicon nitride film formed by the film forming method of the above embodiment has an extremely high dielectric breakdown voltage. Therefore, if this silicon nitride film is used as a gate insulating film of a thin film transistor or an MO5 type integrated circuit element, It is possible to significantly reduce the incidence of insulation defects in thin film transistors and MO5 type integrated circuit devices, and improve their manufacturing yield and reliability.
Since the dielectric breakdown voltage of the semiconductor layer is high, the film thickness can be reduced, so even if the gate voltage applied to the gate electrode is the same, a stronger electric field can be applied to the semiconductor layer to increase the on-current.

また、前記実施例の成膜方法で成膜したシリコン窒化膜
は、その組成比がSl /N−0,83と、化学量論比
より若干シリコンStの量が多い組成となり、したがっ
てこのシリコン窒化膜をゲート絶縁膜とする薄膜トラン
ジスタ等はそのV。
Furthermore, the silicon nitride film formed by the film forming method of the above embodiment has a composition ratio of Sl/N-0.83, which is a composition in which the amount of silicon St is slightly larger than the stoichiometric ratio. Thin film transistors, etc. that use a film as a gate insulating film have that V.

ID特性にヒステリシス性をもつようになるが、シリコ
ン窒化膜の組成比が51 /N−0,83程度では、前
記システリシス性は僅かであるから、薄膜トランジスタ
等の動作特性に大きく影響することはない。
The ID characteristics will have hysteresis, but when the composition ratio of the silicon nitride film is about 51/N-0.83, the systeresis is slight, so it will not greatly affect the operating characteristics of thin film transistors, etc. .

なお、前記実施例では、RF放電のパワー密度を84m
W/cm2としたが、この放電パワー密度は、60〜1
00mW/cm2の範囲であればよく、この範囲の放電
パワー密度で成膜されたシリコン窒化膜は、いずれも第
1図とほぼ同様な絶縁破壊耐圧を示す。
In addition, in the above example, the power density of the RF discharge was set to 84 m
W/cm2, but this discharge power density is 60 to 1
The discharge power density may be in the range of 00 mW/cm2, and any silicon nitride film formed with a discharge power density in this range exhibits a dielectric breakdown voltage substantially similar to that shown in FIG.

〔発明の効果〕〔Effect of the invention〕

本発明のように、プラズマCVD装置によるシリコン窒
化膜の成膜において、RF放電のパワー密度を60〜1
00mW/cm2に制御すれば、高い絶縁破壊耐圧を有
するシリコン窒化膜を得ることができる。
As in the present invention, when forming a silicon nitride film using a plasma CVD apparatus, the power density of RF discharge is set to 60 to 1.
If controlled to 00 mW/cm2, a silicon nitride film having a high dielectric breakdown voltage can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例で成膜したシリコン窒化膜の
絶縁破壊耐圧ヒストグラムを示す図、第2図は従来の成
膜方法で成膜したシリコン窒化膜の絶縁破壊耐圧ヒスト
グラムを示す図、第3図および第4図はシリコン窒化膜
の絶縁破壊耐圧の測定に用いた被検体の平面図およびそ
の一部分の拡大断面図である。 出願人  カシオ計算機株式会社 第 図 印加電界銀4(MV/cry?)
FIG. 1 is a diagram showing a dielectric breakdown voltage histogram of a silicon nitride film formed by an embodiment of the present invention, and FIG. 2 is a diagram showing a dielectric breakdown voltage histogram of a silicon nitride film formed by a conventional film formation method. , FIG. 3, and FIG. 4 are a plan view and an enlarged cross-sectional view of a portion of the test object used for measuring the dielectric breakdown voltage of a silicon nitride film. Applicant Casio Computer Co., Ltd. Figure Applied Electric Field Silver 4 (MV/cry?)

Claims (1)

【特許請求の範囲】[Claims]  プラズマCVD装置によるシリコン窒化膜の成膜にお
いて、RF放電のパワー密度を60〜100mW/cm
^2に制御することを特徴とするシリコン窒化膜の成膜
方法。
When forming a silicon nitride film using a plasma CVD device, the power density of RF discharge is set at 60 to 100 mW/cm.
A method for forming a silicon nitride film characterized by controlling the film to ^2.
JP2107376A 1990-04-25 1990-04-25 Method of forming silicon nitride film Pending JPH046834A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2107376A JPH046834A (en) 1990-04-25 1990-04-25 Method of forming silicon nitride film
US07/690,816 US5284789A (en) 1990-04-25 1991-04-23 Method of forming silicon-based thin film and method of manufacturing thin film transistor using silicon-based thin film
EP91106621A EP0454100B1 (en) 1990-04-25 1991-04-24 Method of forming silicon nitride thin film and method of manufacturing thin film transistor using silicon nitride thin film
DE69128210T DE69128210T2 (en) 1990-04-25 1991-04-24 Methods of manufacturing silicon nitride thin films and methods of manufacturing a thin film transistor using silicon nitride thin films
KR1019910006715A KR940008356B1 (en) 1990-04-25 1991-04-25 Method of film formation of silicon based thin film and method of manufacturing thin film transistor using the thin film
US07/975,282 US5367179A (en) 1990-04-25 1992-11-12 Thin-film transistor having electrodes made of aluminum, and an active matrix panel using same
US08/004,641 US5243202A (en) 1990-04-25 1993-01-12 Thin-film transistor and a liquid crystal matrix display device using thin-film transistors of this type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2107376A JPH046834A (en) 1990-04-25 1990-04-25 Method of forming silicon nitride film

Publications (1)

Publication Number Publication Date
JPH046834A true JPH046834A (en) 1992-01-10

Family

ID=14457539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2107376A Pending JPH046834A (en) 1990-04-25 1990-04-25 Method of forming silicon nitride film

Country Status (1)

Country Link
JP (1) JPH046834A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130256266A1 (en) * 2012-03-30 2013-10-03 Andreas Fischer Methods and apparatuses for effectively reducing gas residence time in a plasma processing chamber

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62200768A (en) * 1986-02-27 1987-09-04 Fujitsu Ltd Manufacture of thin film transistor
JPS62291064A (en) * 1986-06-11 1987-12-17 Oki Electric Ind Co Ltd Manufacture of thin film transistor
JPS6350477A (en) * 1986-08-19 1988-03-03 Fujitsu Ltd Method for forming thin film devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62200768A (en) * 1986-02-27 1987-09-04 Fujitsu Ltd Manufacture of thin film transistor
JPS62291064A (en) * 1986-06-11 1987-12-17 Oki Electric Ind Co Ltd Manufacture of thin film transistor
JPS6350477A (en) * 1986-08-19 1988-03-03 Fujitsu Ltd Method for forming thin film devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130256266A1 (en) * 2012-03-30 2013-10-03 Andreas Fischer Methods and apparatuses for effectively reducing gas residence time in a plasma processing chamber
US9299541B2 (en) * 2012-03-30 2016-03-29 Lam Research Corporation Methods and apparatuses for effectively reducing gas residence time in a plasma processing chamber

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